Patents by Inventor Chung-Ru Wu

Chung-Ru Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11757615
    Abstract: A device includes feed-forward clock circuitry to provide a receiver (RX) clock to a sampler circuit that samples a data lane of a set of RX data lanes, the feed-forward clock circuitry having a temperature-induced delay. The device also includes an RX phase-locked loop (PLL) coupled between the feed-forward clock circuitry and the sampler circuit. The RX PLL includes a phase interpolator positioned in a feedback path of the RX PLL. The phase interpolator has a negative delay that matches the temperature-induced delay of the feed-forward clock circuitry to cause the sampler circuit to cancel out the common noise shared between the feed-forward clock circuitry and the data lane.
    Type: Grant
    Filed: November 8, 2021
    Date of Patent: September 12, 2023
    Assignee: NVIDIA Corporation
    Inventors: Yi-Chieh Huang, Ying Wei, Chung-Ru Wu, Bo-Yu Chen, Haiming Tang
  • Publication number: 20230141897
    Abstract: A device includes feed-forward clock circuitry to provide a receiver (RX) clock to a sampler circuit that samples a data lane of a set of RX data lanes, the feed-forward clock circuitry having a temperature-induced delay. The device also includes an RX phase-locked loop (PLL) coupled between the feed-forward clock circuitry and the sampler circuit. The RX PLL includes a phase interpolator positioned in a feedback path of the RX PLL. The phase interpolator has a negative delay that matches the temperature-induced delay of the feed-forward clock circuitry to cause the sampler circuit to cancel out the common noise shared between the feed-forward clock circuitry and the data lane.
    Type: Application
    Filed: November 8, 2021
    Publication date: May 11, 2023
    Inventors: Yi-Chieh Huang, Ying Wei, Chung-Ru Wu, Bo-Yu Chen, Haiming Tang
  • Publication number: 20220314391
    Abstract: A polishing pad adapted for polishing an object and having a polishing track region is provided. The polishing pad includes a polishing layer and an adhesive layer. The polishing layer has a polishing surface and a rough bottom surface opposite to each other, and the rough bottom surface includes a plurality of discontinuous dents. The adhesive layer is adhered to the rough bottom surface.
    Type: Application
    Filed: March 17, 2022
    Publication date: October 6, 2022
    Applicant: IV Technologies CO., Ltd.
    Inventors: Kun-Che Pai, WEI CHEN LIU, Chung-Ru Wu
  • Patent number: 10828745
    Abstract: A polishing pad is provided. The polishing pad, disposed on a polishing platen and suitable for a polishing process, includes a polishing layer, an adhesive layer and at least one adhesion-reducing interface layer. The adhesive layer is disposed between the polishing layer and the polishing platen. The at least one adhesion-reducing interface layer is disposed between the adhesive layer and the polishing layer and/or disposed between the adhesive layer and the polishing platen. An area of the at least one adhesion-reducing interface layer is smaller than an area of the adhesive layer.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: November 10, 2020
    Assignee: IV Technologies CO., Ltd.
    Inventors: Chung-Ru Wu, Yu-Hao Pan, Kun-Che Pai, Chun-Ming Ting
  • Publication number: 20180200864
    Abstract: A polishing pad is provided. The polishing pad, disposed on a polishing platen and suitable for a polishing process, includes a polishing layer, an adhesive layer and at least one adhesion-reducing interface layer. The adhesive layer is disposed between the polishing layer and the polishing platen. The at least one adhesion-reducing interface layer is disposed between the adhesive layer and the polishing layer and/or disposed between the adhesive layer and the polishing platen. An area of the at least one adhesion-reducing interface layer is smaller than an area of the adhesive layer.
    Type: Application
    Filed: January 12, 2018
    Publication date: July 19, 2018
    Applicant: IV Technologies CO., Ltd.
    Inventors: Chung-Ru Wu, Yu-Hao Pan, Kun-Che Pai, Chun-Ming Ting
  • Patent number: 6743075
    Abstract: The present invention relates to a method for determining rapidly and accurately the polishing time of a chemical mechanical polishing process for polishing target wafers to avoid any problems of under-polishing or over-polishing. An aspect of the present invention is directed to a method for determining a chemical mechanical polishing time for removing a target polishing thickness H from an uneven surface of a target wafer. The method comprises polishing a control wafer by a chemical mechanical polishing to obtain a progressive relationship of polishing thickness and respective polishing time therefor. A first polishing time T1 is determined for removing a first thickness H1 from the target wafer, in which the first thickness H1 with substantially the uneven surface removed is smaller than the target polishing thickness H of the target wafer to be removed.
    Type: Grant
    Filed: January 15, 2003
    Date of Patent: June 1, 2004
    Assignee: Mosel Vitelic, Inc.
    Inventors: Chun-Te Lin, Shan-An Liu, Chung-Ru Wu, Ming-Hsien Lu
  • Publication number: 20030186621
    Abstract: The present invention relates to a method for determining rapidly and accurately the polishing time of a chemical mechanical polishing process for polishing target wafers to avoid any problems of under-polishing or over-polishing. An aspect of the present invention is directed to a method for determining a chemical mechanical polishing time for removing a target polishing thickness H from an uneven surface of a target wafer. The method comprises polishing a control wafer by a chemical mechanical polishing to obtain a progressive relationship of polishing thickness and respective polishing time therefor. A first polishing time T1 is determined for removing a first thickness H1 from the target wafer, in which the first thickness H1 with substantially the uneven surface removed is smaller than the target polishing thickness H of the target wafer to be removed.
    Type: Application
    Filed: January 15, 2003
    Publication date: October 2, 2003
    Applicant: MOSEL VITELIC, INC., A Taiwanese Corporation
    Inventors: Chun-Te Lin, Shan-An Liu, Chung-Ru Wu, Ming-Hsien Lu