Abstract: A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal.

Abstract: A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal

Abstract: A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal.

Abstract: A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal

Abstract: A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal.

Abstract: A method for programming memory cells of a selected word line has steps of: providing a first word line programming signal being at plurality of voltage levels in different programming slots of a current programming operation to the memory cells of the selected word line, wherein the first word line programming signal is a ramping voltage signal; and providing a second line programming signal being at plurality of voltage levels in different programming slots of a next programming operation to the memory cells of the selected word line, wherein the second word line programming signal is another one ramping voltage signal; wherein the highest voltage levels of the first and second word line programming signals are identical to each other, and a number of the voltage levels of the first word line programming signal is larger than that of the second word line programming signal.

Abstract: A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal

Abstract: A method of booting a system with a non-volatile memory device includes at least the following steps: when the system is powered on, reading a status flag of at least a memory block of the non-volatile memory device, wherein the status flag indicates whether an erase operation applied to the memory block is successfully completed; selectively performing a leakage calibration process upon the memory block according to the status flag; and booting the system according to a boot code stored in the non-volatile memory device.

Abstract: A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal.

Abstract: A method for programming memory cells of a selected word line has steps of: providing a first word line programming signal being at plurality of voltage levels in different programming slots of a current programming operation to the memory cells of the selected word line, wherein the first word line programming signal is a ramping voltage signal; and providing a second line programming signal being at plurality of voltage levels in different programming slots of a next programming operation to the memory cells of the selected word line, wherein the second word line programming signal is another one ramping voltage signal; wherein the highest voltage levels of the first and second word line programming signals are identical to each other, and a number of the voltage levels of the first word line programming signal is larger than that of the second word line programming signal.

Abstract: A method of booting a system with a non-volatile memory device includes at least the following steps: when the system is powered on, reading a status flag of at least a memory block of the non-volatile memory device, wherein the status flag indicates whether an erase operation applied to the memory block is successfully completed; selectively performing a leakage calibration process upon the memory block according to the status flag; and booting the system according to a boot code stored in the non-volatile memory device.

Abstract: A charge pump circuit comprises a first booster set, a second booster group, and a detecting circuit. The first booster set receives a supply voltage and generates a first output voltage. The detecting circuit generates a detecting signal depending on the voltage level of the first output voltage. The second booster group receives the supply voltage and generates the first output voltage or a second output voltage according to the detecting signal. The second booster group is composed of a plurality of booster sets connected in parallel, wherein each booster set comprises a plurality of charge pump stages and a plurality of switch units. The number of serially-connected charge pump stages of each booster set in the second booster group is controlled by the plurality of switch units according to the stable voltage levels of the first and second output voltages.

Abstract: A method of trimming a reference cell in a semiconductor memory device comprises the steps of: generating a reference current based on a bias voltage applied to the reference cell; generating a first current and a second current based on the value of a control voltage and the resistance of a precision resistor disposed outside the semiconductor memory device; comparing the reference current with the first current; comparing the reference current with the second current; programming the reference cell if the value of the reference current is greater than that of the first current; and erasing the reference cell if the value of the reference current is less than that of the second current. The value of the second current is less than that of the first current.

Abstract: A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal.

Abstract: A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal.

Abstract: A method of trimming a reference cell in a semiconductor memory device comprises the steps of: generating a reference current based on a bias voltage applied to the reference cell; generating a first current and a second current based on the value of a control voltage and the resistance of a precision resistor disposed outside the semiconductor memory device; comparing the reference current with the first current; comparing the reference current with the second current; programming the reference cell if the value of the reference current is greater than that of the first current; and erasing the reference cell if the value of the reference current is less than that of the second current. The value of the second current is less than that of the first current.

Abstract: A method for programming a plurality of memory cells of a nonvolatile semiconductor memory device comprises the steps of: sequentially performing a plurality of divide-by-2 operations on the plurality of memory cells; generating a plurality of reduced groups from the memory cells after each of the divide-by-2 operations is performed; sequentially programming the memory cells of each reduced group; generating a final group after a final divide-by-2 operation is performed; programming the memory cells of the final group; and verifying whether the memory cells of the final group are completely programmed. The memory cells of the final group are composed of all the memory cells of the nonvolatile semiconductor memory device and the verifying step is only performed after the step of programming the memory cells of the final group.

Abstract: A charge pump circuit comprises a first booster set, a second booster group, and a detecting circuit. The first booster set receives a supply voltage and generates a first output voltage. The detecting circuit generates a detecting signal depending on the voltage level of the first output voltage. The second booster group receives the supply voltage and generates the first output voltage or a second output voltage according to the detecting signal. The second booster group is composed of a plurality of booster sets connected in parallel, wherein each booster set comprises a plurality of charge pump stages and a plurality of switch units. The number of serially-connected charge pump stages of each booster set in the second booster group is controlled by the plurality of switch units according to the stable voltage levels of the first and second output voltages.

Abstract: A method for programming a plurality of memory cells of a nonvolatile semiconductor memory device comprises the steps of: sequentially performing a plurality of divide-by-2 operations on the plurality of memory cells; generating a plurality of reduced groups from the memory cells after each of the divide-by-2 operations is performed; sequentially programming the memory cells of each reduced group; generating a final group after a final divide-by-2 operation is performed; programming the memory cells of the final group; and verifying whether the memory cells of the final group are completely programmed. The memory cells of the final group are composed of all the memory cells of the nonvolatile semiconductor memory device and the verifying step is only performed after the step of programming the memory cells of the final group.

Abstract: A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal.