Abstract: A method includes performing a first laser shot on a first portion of a top surface of a first package component. The first package component is over a second package component, and a first solder region between the first package component and the second package component is reflowed by the first laser shot. After the first laser shot, a second laser shot is performed on a second portion of the top surface of the first package component. A second solder region between the first package component and the second package component is reflowed by the second laser shot.

Abstract: A semiconductor device including a singulated structure and an optical fiber assembly is provided. The singulated structure includes a photonic die, an electronic die connected to the photonic die and an optical element over the photonic die. The optical fiber assembly is disposed on a top of the singulated structure and includes a holder and an optical fiber structure. The holder keeps an air gap from the optical element. The optical fiber structure is carried by the holder and configured to be optically communicated with the photonic die through the optical element.

Abstract: A molding apparatus is configured for molding a semiconductor device and includes a lower mold and an upper mold. The lower mold is configured to carry the semiconductor device. The upper mold is disposed above the lower mold for receiving the semiconductor device and includes a mold part and a dynamic part. The mold part is configured to cover the upper surface of the semiconductor device. The dynamic part is disposed around a device receiving region of the upper mold and configured to move relatively to the mold part. A molding method and a molded semiconductor device are also provided.

Abstract: An embodiment includes a first package component including a first integrated circuit die and a first encapsulant at least partially surrounding the first integrated circuit die. The device also includes a redistribution structure on the first encapsulant and coupled to the first integrated circuit die. The device also includes a first thermal module coupled to the first integrated circuit die. The device also includes a second package component bonded to the first package component, the second package component including a power module attached to the first package component, the power module including active devices. The device also includes a second thermal module coupled to the power module. The device also includes a mechanical brace extending from a top surface of the second thermal module to a bottom surface of the first thermal module, the mechanical brace physically contacting the first thermal module and the second thermal module.

Abstract: A method includes bonding a first device die to a second device die, encapsulating the first device die in a first encapsulant, performing a backside grinding process on the second device die to reveal through-vias in the second device die, and forming first electrical connectors on the second device die to form a package. The package includes the first device die and the second device die. The method further includes encapsulating the first package in a second encapsulant, and forming an interconnect structure overlapping the first package and the second encapsulant. The interconnect structure comprises second electrical connectors.

Abstract: A memory device including a base chip and a memory cube mounted on and connected with the base chip is described. The memory cube includes multiple stacked tiers, and each tier of the multiple stacked tiers includes semiconductor chips laterally wrapped by an encapsulant and a redistribution structure. The semiconductor chips of the multiple stacked tiers are electrically connected with the base chip through the redistribution structures in the multiple stacked tiers. The memory cube includes a thermal path structure extending through the multiple stacked tiers and connected to the base chip. The thermal path structure has a thermal conductivity larger than that of the encapsulant. The thermal path structure is electrically isolated from the semiconductor chips in the multiple stacked tiers and the base chip.

Abstract: A package structure includes a bottom plate, a semiconductor package, a top plate, a screw and an anti-loosening coating. The semiconductor package is disposed over the bottom plate. The top plate is disposed over the semiconductor package, and includes an internal thread in a screw hole of the top plate. The screw penetrates through the bottom plate, the semiconductor package and the top plate, and includes an external thread. The external thread of the screw is engaged to the internal thread of the top plate, and the anti-loosening coating is adhered between the external thread and the internal thread.

Abstract: A method includes placing a first package component over a vacuum boat, wherein the vacuum boat comprises a hole, and wherein the first package component covers the hole. A second package component is placed over the first package component, wherein solder regions are disposed between the first and the second package components. The hole is vacuumed, wherein the first package component is pressed by a pressure against the vacuum boat, and wherein the pressure is generated by a vacuum in the hole. When the vacuum in the hole is maintained, the solder regions are reflowed to bond the second package component to the first package component.

Abstract: A semiconductor package includes a first die; a first redistribution structure over the first die, the first redistribution structure being conterminous with the first die; a second die over the first die, a first portion of the first die extending beyond a lateral extent of the second die; a conductive pillar over the first portion of the first die and laterally adjacent to the second die, the conductive pillar electrically coupled to first die; a molding material around the first die, the second die, and the conductive pillar; and a second redistribution structure over the molding material, the second redistribution structure electrically coupled to the conductive pillar and the second die.

Abstract: In accordance with some embodiments a via is formed over a semiconductor device, wherein the semiconductor device is encapsulated within an encapsulant 129. A metallization layer and a second via are formed over and in electrical connection with the first via, and the metallization layer and the second via are formed using the same seed layer. Embodiments include fully landed vias, partially landed vias in contact with the seed layer, and partially landed vias not in contact with the seed layer.

Abstract: In an embodiment, a device includes: a package component including: a first integrated circuit die; an encapsulant at least partially surrounding the first integrated circuit die; a redistribution structure on the encapsulant, the redistribution structure physically and electrically coupling the first integrated circuit die; a first module socket attached to the redistribution structure; an interposer attached to the redistribution structure adjacent the first module socket, the outermost extent of the interposer extending beyond the outermost extent of the redistribution structure; and an external connector attached to the interposer.

Abstract: A semiconductor structure includes a die and a first connector. The first connector is disposed on the die. The first connector includes a first connecting housing, a first connecting element and a first connecting portion. The first connecting element is electrically connected to the die and disposed at a first side of the first connecting housing. The first connecting portion is disposed at a second side different from the first side of the first connecting housing, wherein the first connecting portion is one of a hole and a protrusion with respect to a surface of the second side of the first connecting housing.

Abstract: A package includes a package substrate, an interposer over and bonded to the package substrate, a first wafer over and bonding to the interposer, and a second wafer over and bonding to the first wafer. The first wafer has independent passive device dies therein. The second wafer has active device dies therein.

Abstract: A package structure and a method of forming the same are provided. The package structure includes a first die, a second die, a first encapsulant, and a buffer layer. The first die and the second die are disposed side by side. The first encapsulant encapsulates the first die and the second die. The second die includes a die stack encapsulated by a second encapsulant encapsulating a die stack. The buffer layer is disposed between the first encapsulant and the second encapsulant and covers at least a sidewall of the second die and disposed between the first encapsulant and the second encapsulant. The buffer layer has a Young's modulus less than a Young's modulus of the first encapsulant and a Young's modulus of the second encapsulant.

Abstract: A semiconductor package includes electric integrated circuit dies, photoelectric integrated circuit dies, and an inter-chip waveguide. The electric integrated circuit dies are laterally encapsulated by a first insulating encapsulant. The photoelectric integrated circuit dies are laterally encapsulated by a second insulating encapsulant. Each one of photoelectric integrated circuit dies includes an optical input/output terminal. The inter-chip waveguide is disposed over the second insulating encapsulant, wherein the photoelectric integrated circuit dies are optically communicated with each other through the inter-chip waveguide.

Abstract: A structure includes a first via and a first conductive line embedded in a first dielectric layer and spaced apart from each other by the first dielectric layer. A first metal pattern disposed on the first via and embedded in a second dielectric layer. A first conductive via disposed on the first conductive line and embedded in the second dielectric layer. The first metal pattern and the first conductive via are spaced apart from each other and are located on a first horizontal level, and the first metal pattern has an open ring shape. A second via disposed on the first metal pattern and embedded in a third dielectric layer. An inductor structure including the first via, the first metal pattern, and the second via.

Abstract: A method includes performing a first laser shot on a first portion of a top surface of a first package component. The first package component is over a second package component, and a first solder region between the first package component and the second package component is reflowed by the first laser shot. After the first laser shot, a second laser shot is performed on a second portion of the top surface of the first package component. A second solder region between the first package component and the second package component is reflowed by the second laser shot.

Abstract: A semiconductor package including a circuit substrate, an interposer structure, a plurality of dies, and an insulating encapsulant is provided. The interposer structure is disposed on the circuit substrate. The plurality of dies is disposed on the interposer structure, wherein the plurality of dies is electrically connected to the circuit substrate through the interposer structure. The insulating encapsulant is disposed on the circuit substrate, wherein the insulating encapsulant surrounds the plurality of dies and the interposer structure and encapsulates at least the interposer structure, the insulating encapsulant has a groove that surrounds the interposer structure and the plurality of dies, and the interposer structure and the plurality of dies are confined to be located within the groove.

Abstract: A chip package structure includes an interposer structure that contains a package-side redistribution structure, an interposer core assembly, and a die-side redistribution structure. The interposer core assembly includes at least one silicon substrate interposer, and each of the at least one silicon substrate interposer includes a respective silicon substrate, a respective set of through-silicon via (TSV) structures vertically extending through the respective silicon substrate, a respective set of interconnect-level dielectric layers embedding a respective set of metal interconnect structures, and a respective set of metal bonding structures that are electrically connected to the die-side redistribution structure. The chip package structure includes at least two semiconductor dies that are attached to the die-side redistribution structure, and an epoxy molding compound (EMC) multi-die frame that laterally encloses the at least two semiconductor dies.

Abstract: A method includes forming an adhesive layer over a carrier, forming a sacrificial layer over the adhesive layer, forming through-vias over the sacrificial layer, and placing a device die over the sacrificial layer. The Method further includes molding and planarizing the device die and the through-vias, de-bonding the carrier by removing the adhesive layer, and removing the sacrificial layer.