Patents by Inventor Chung-shiang Wu

Chung-shiang Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • INTEGRATED CIRCUITS WITH PROGRAMMABLE GATE TIMING SIGNAL GENERATION FOR POWER CONVERTERS AND APPARATUS COMPRISING THE SAME
    Publication number: 20200244166
    Abstract: An apparatus is disclosed that includes a semiconductor device to control a power converter having two or more power FETs. The semiconductor device includes a gate signal generator configured to produce two or more gate signals able to drive the two or more FETs. The gate signal generator has programmable timing configuration parameters to control operation of the two or more gate signals, wherein the timing configuration parameters are digitally programmed via a memory in the semiconductor device. The memory may be implemented with fuses, other non-volatile memory or volatile memory. The parameters may be fixed or updated during a lifetime of the apparatus. A serial-to-parallel conversion may be used to input the parameters. Optimization methods may be performed to determine parameters considered to be optimal. The apparatus may also include the power converter.
    Type: Application
    Filed: January 25, 2019
    Publication date: July 30, 2020
    Inventors: Xin Zhang, Todd Edward Takken, Chung-shiang Wu, Robert Matthew Senger, Rudolf Adriaan Haring, Martin Ohmacht
  • Integrated circuits with programmable gate timing signal generation for power converters and apparatus comprising the same
    Patent number: 10707755
    Abstract: An apparatus is disclosed that includes a semiconductor device to control a power converter having two or more power FETs. The semiconductor device includes a gate signal generator configured to produce two or more gate signals able to drive the two or more FETs. The gate signal generator has programmable timing configuration parameters to control operation of the two or more gate signals, wherein the timing configuration parameters are digitally programmed via a memory in the semiconductor device. The memory may be implemented with fuses, other non-volatile memory or volatile memory. The parameters may be fixed or updated during a lifetime of the apparatus. A serial-to-parallel conversion may be used to input the parameters. Optimization methods may be performed to determine parameters considered to be optimal. The apparatus may also include the power converter.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: July 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Xin Zhang, Todd Edward Takken, Chung-shiang Wu, Robert Matthew Senger, Rudolf Adriaan Haring, Martin Ohmacht