Patents by Inventor Chung Shih
Chung Shih has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12188734Abstract: A water supply device (10) and a tube connector structure (2) thereof, which are used for an electronic device (100) having a water inlet (101) and a water outlet (102), are disclosed. The tube connector structure (2) includes a connecting plate (21) and two tube connector plugs (22) passing through and fixed to the connecting plate (21). One of the tube connector plugs (22) is connected with the water inlet (101), and the other one of the tube connector plugs (22) is connected with the water outlet (102). Therefore, advantages of rapid connection and disconnection between the water supply device (10) and the tube connector structure (2) and saving time and labor in assembling may be accomplished.Type: GrantFiled: October 3, 2022Date of Patent: January 7, 2025Assignee: UNIWILL TECHNOLOGY INC.Inventors: Chih-Hsien Chen, Yu-Cheng Shih, Pon-Chung Chien, Chieh-Hui Chen, Ying-Fu Chou
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Publication number: 20250008743Abstract: A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, a first ultra low-k (ULK) dielectric layer on the first MTJ and the second MTJ, a passivation layer on the first ULK dielectric layer, and a second ULK dielectric layer on the passivation layer.Type: ApplicationFiled: September 15, 2024Publication date: January 2, 2025Applicant: UNITED MICROELECTRONICS CORP.Inventors: Kun-Ju Li, Tai-Cheng Hou, Hsin-Jung Liu, Fu-Yu Tsai, Bin-Siang Tsai, Chau-Chung Hou, Yu-Lung Shih, Ang Chan, Chih-Yueh Li, Chun-Tsen Lu
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Publication number: 20240405123Abstract: A high-voltage device structure and methods of forming the same are described. In some embodiments, the structure includes a deep well region of a first conductivity type disposed in a substrate, a doped region disposed on the deep well region; a well region of the first conductivity type surrounding the deep well region and the doped region; a source region disposed on the well region, a drain region disposed on the doped region, and a first pickup region of the first conductivity type disposed on the well region. The first pickup region is laterally in contact with the source region, and the first pickup region, the well region, and the deep well region are electrically connected.Type: ApplicationFiled: June 5, 2023Publication date: December 5, 2024Inventors: Chien-Ming KU, Wei-Jen CHANG, Wen-Hsing HSIEH, Ming-Yang HSU, Chia-Chi HO, Chung-Shih CHIANG
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Patent number: 12152101Abstract: Disclosed are support-activators and catalyst compositions comprising the support-activators for polymerizing olefins in which the support-activator includes clay heteroadduct, prepare from a colloidal phyllosilicate such as a colloidal smectite clay, which is chemically-modified with a heterocoagulation agent. By limiting the amount of heterocoagulation reagent relative to the colloidal smectite clay as described herein, the smectite heteroadduct support-activator is a porous and amorphous solid which can be readily isolated from the resulting slurry by a conventional filtration process, and which can activate metallocenes and related catalysts toward olefin polymerization. Related compositions and processes are disclosed.Type: GrantFiled: October 11, 2023Date of Patent: November 26, 2024Assignee: FORMOSA PLASTICS CORPORATION, U.S.A.Inventors: Michael D Jensen, Kevin Chung, Daoyong Wang, Wei-Chun Shih, Guangxue Xu, Chih-Jian Chen, Charles R. Johnson, II, Mary Lou Cowen
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Publication number: 20240387418Abstract: A semiconductor device includes a bottom wafer, a top wafer bonded to the bottom wafer, a first dielectric layer, a second dielectric layer, a deep via conductor structure, and a connection pad. The top wafer includes a first interconnection structure. The first dielectric layer is disposed on the top wafer. The second dielectric layer is disposed on the first dielectric layer. The deep via conductor structure penetrates through the second dielectric layer and the first dielectric layer and is connected with the first interconnection structure. The connection pad is disposed on the second dielectric layer and the deep via conductor structure. A first portion of the second dielectric layer is sandwiched between the connection pad and the first dielectric layer. A second portion of the second dielectric layer is connected with the first portion, and a thickness of the second portion is less than a thickness of the first portion.Type: ApplicationFiled: June 14, 2023Publication date: November 21, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Yu-Chun Chen, Yu-Ping Wang, I-Ming Tseng, Yi-An Shih, Chung-Sung Chiang, Chiu-Jung Chiu
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Patent number: 12148238Abstract: An electronic circuit adapted to drive a display panel is provided. The electronic circuit includes a touch sensing circuit, a fingerprint sensing circuit and a display driving circuit. The touch sensing circuit senses a touch of a finger and determines a first area corresponding to the touch on the display panel. The fingerprint sensing circuit senses a fingerprint image of the finger corresponding to the first area. The display driving circuit drives pixels of the first area with respective first gray levels and pixels of a second area outside the first area with respective second gray levels. The display driving circuit processes respective third gray levels to obtain the respective first gray levels or the respective second gray levels. The display driving circuit generates gamma voltages corresponding to the respective first gray levels and the respective second gray levels according to a same gamma curve.Type: GrantFiled: April 26, 2023Date of Patent: November 19, 2024Assignee: Novatek Microelectronics Corp.Inventors: Wei-Lun Shih, Tzu-Wen Hsieh, Huan-Teng Cheng, Huang-Chin Tang, Yueh-Teng Mai, Shi-Hao Huang, Jung-Chung Lee
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Publication number: 20240377720Abstract: A lithography mask includes a substrate that contains a low thermal expansion material (LTEM). The lithography mask also includes a reflective structure disposed over the substrate. The reflective structure includes a first layer and a second layer disposed over the first layer. At least the second layer is porous. The mask is formed by forming a multilayer reflective structure over the LTEM substrate, including forming a plurality of repeating film pairs, where each film pair includes a first layer and a porous second layer. A capping layer is formed over the multilayer reflective structure. An absorber layer is formed over the capping layer.Type: ApplicationFiled: July 22, 2024Publication date: November 14, 2024Inventors: Chih-Tsung Shih, Shih-Chang Shih, Li-Jui Chen, Po-Chung Cheng
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Publication number: 20240371758Abstract: A method for fabricating a semiconductor device includes the steps of first bonding a top wafer to a bottom wafer, in which the top wafer has a first metal interconnection including a first barrier layer exposing from a bottom surface of the top wafer. Next, a dielectric layer is formed on the bottom surface of the top wafer and then a second metal interconnection is formed in the dielectric layer and connected to the first metal interconnection, in which the second metal interconnection includes a second barrier layer and the first barrier layer and the second barrier layer include a H-shape altogether.Type: ApplicationFiled: May 31, 2023Publication date: November 7, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Yu-Chun Chen, Yu-Ping Wang, I-Ming Tseng, Yi-An Shih, Chung-Sung Chiang, Chiu-Jung Chiu
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Publication number: 20240360720Abstract: A cord divider is positioned on both sides of the cord winder of the control box of a cordless window curtain. Each cord divider is equipped with protrusions and crosspieces. When the cords are pulled out from the cord divider, the cords do not tangle or knot. The cords are wound up on the driving gear set, and the driving cord device prevents the cords from overlapping and causing uneven heights on both sides of the curtain. The use of cylinders in the cord dividers prevents excessive friction of the cords during use. There is no need to change the current cooperation way between the cords and the cord winder.Type: ApplicationFiled: July 12, 2023Publication date: October 31, 2024Inventors: WEN YING LIANG, Sheng Ying HSU, Chien Chih HUANG, Wu Chung NIEN, Ming Chu CHIANG, Wei Ming SHIH
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Publication number: 20240357943Abstract: A method for fabricating semiconductor device includes the steps of forming an inter-metal dielectric (IMD) layer on a substrate, forming a trench in the IMD layer, forming a synthetic antiferromagnetic (SAF) layer in the trench, forming a metal layer on the SAF layer, planarizing the metal layer and the SAF layer to form a metal interconnection, and forming a magnetic tunneling junction (MTJ) on the metal interconnection.Type: ApplicationFiled: June 30, 2024Publication date: October 24, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chiu-Jung Chiu, Ya-Sheng Feng, I-Ming Tseng, Yi-An Shih, Yu-Chun Chen, Yi-Hui Lee, Chung-Liang Chu, Hsiu-Hao Hu
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Patent number: 12127413Abstract: A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, a first ultra low-k (ULK) dielectric layer on the first MTJ and the second MTJ, a passivation layer on the first ULK dielectric layer, and a second ULK dielectric layer on the passivation layer.Type: GrantFiled: February 23, 2023Date of Patent: October 22, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Kun-Ju Li, Tai-Cheng Hou, Hsin-Jung Liu, Fu-Yu Tsai, Bin-Siang Tsai, Chau-Chung Hou, Yu-Lung Shih, Ang Chan, Chih-Yueh Li, Chun-Tsen Lu
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Patent number: 12117661Abstract: The present disclosure provides a photonic integrated circuit chip. The photonic integrated circuit chip comprises a plurality of connection ports, multiple polarization beam splitting structures, a photodetector structure, an interleaver and a modulator. The plurality of connection ports are used to receive a plurality of first optical signals to the photonic integrated circuit chip. The multiple polarization beam splitting structures each are used to split the first optical signal passing through the polarization beam splitting structure into a first mode optical signal and a second mode optical signal. The photodetector structure comprises a first component for split beam and a second component for split beam. The interleaver is used to transfer the first mode optical signal or the second mode optical signal to the second component for split beam. The modulator is used to transfer second optical signals with different wavelengths to the interleaver.Type: GrantFiled: September 3, 2021Date of Patent: October 15, 2024Assignee: Molex, LLCInventors: Li-Chi Yang, Bing-Hao Shih, Chih-Chung Wu, Zuon-Min Chuang
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Publication number: 20240336210Abstract: An automotive decorative panel includes a decorative film, a touch icon component, and a light source system. The decorative film has an optical density between 0.2 and 2.0 and includes a substrate and a decorative layer disposed on the substrate. The touch icon component is disposed under the decorative film and includes a light-shielding pattern layer having an optical density between 3.5 and 6.0, a light diffusion layer disposed under the light-shielding pattern layer, and a touch layer. The light-shielding pattern layer has a pattern area that is light-permeable and a peripheral area that is light-impermeable. The touch layer is disposed on a side of the light-shielding pattern layer or between the decorative film and the light-shielding pattern layer. The light source system is disposed on a side of the touch icon component and configured to emit light toward the touch icon component.Type: ApplicationFiled: April 6, 2023Publication date: October 10, 2024Inventors: Ding Gui Zeng, Le Le Su, Chung Chieh Wu, Yun Chien Lo, Chun Yong Zhang, Tai-Shih Cheng
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Publication number: 20240339756Abstract: A planar transparent antenna structure is provided. The planar transparent antenna structure includes a dielectric substrate, a radiation patch conductive layer, a parasitic patch conductive layer and a ground conductive layer. The radiation patch conductive layer is disposed on the dielectric substrate. The radiation patch conductive layer is a ring structure. The parasitic patch conductive layer is disposed on the dielectric substrate. The ground conductive layer is disposed on the dielectric substrate. The radiation patch conductive layer, the parasitic patch conductive layer and the ground conductive layer are composed of a plurality of wires interconnected and connected with each other and are light-transmissive.Type: ApplicationFiled: April 2, 2024Publication date: October 10, 2024Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Bing-Syun LI, Li-Yang TSAI, Kuang-Hui SHIH, Ruo-Lan CHANG, Wei-Chung CHEN
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Publication number: 20240337150Abstract: A method for forming a honeycomb curtain and includes a weaving process, a fixing process, a gluing process, a stacking process and a cutting process. The honeycomb curtain includes multiple netted tubes, and each netted tube includes an upper portion and a lower portion. The central portion of each of the upper and lower portions is woven to form a tight-woven structure. Two sides of each of the central portions are woven to form a sparse-woven structure to form the upper portion to be a breathable first semi-transparent strip and to form the lower portion to be a second semi-transparent strip. The outer corner of each of the upper and lower portions are woven to form another tight-woven structure. The central portions of each of the netted tubes are applied with glue on respective outer face thereof. The netted tubes are stacked and pressed to form a layered structure.Type: ApplicationFiled: November 28, 2023Publication date: October 10, 2024Inventors: WEN YING LIANG, Sheng Ying HSU, Chien Chih HUANG, Wu Chung NIEN, Ming Chu CHIANG, Wei Ming SHIH
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Publication number: 20240339758Abstract: A planar transparent antenna structure is provided. The planar transparent antenna structure includes a dielectric substrate, a radiation conductive layer and a ground conductive layer. The dielectric substrate has a first surface and a second surface. The radiation conductive layer is disposed on the first surface of the dielectric substrate. The ground conductive layer is disposed on the second surface of the dielectric substrate. The radiation conductive layer and the ground conductive layer are composed of a plurality of wires connected in a mesh manner. Each of the wires is composed of a plurality of grid lines connected in a mesh manner.Type: ApplicationFiled: April 3, 2024Publication date: October 10, 2024Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Bing-Syun LI, Li-Yang TSAI, Kuang-Hui SHIH, Ruo-Lan CHANG, Kung-Ching CHU, Wei-Chung CHEN
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Publication number: 20240340565Abstract: A speaker module, including: a speaker enclosure, including: a recessed portion; a transducer, including: a top surface; a bottom surface; a perimeter surface positioned between the top surface and the bottom surface; a rubber cap including: a top side; a bottom side; and edges extending between the top side and the bottom side, wherein the edges define an inside perimeter of the rubber cap and include a slot extending along the inside perimeter of the rubber cap, wherein, the transducer is coupled to the rubber cap such that the rubber cap surrounds the transducer and the perimeter surface of the transducer is positioned within the slot of the plurality of edges of the rubber cap, wherein, the transducer is coupled to the speaker enclosure such that the transducer is positioned within the recessed portion of the speaker enclosure and the rubber cap is positioned between the transducer and the speaker.Type: ApplicationFiled: April 4, 2023Publication date: October 10, 2024Inventors: CHIA-HUNG SHIH, CHIN-CHUNG WU, CHIEN-YU HUANG, CHUN-KAI TZENG
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Patent number: 12113046Abstract: A method for preparing a semiconductor device includes providing an integrated circuit die having a bond pad. The bond pad includes aluminum (Al). The method also includes etching a top portion of the bond pad to form a recess, and bonding a wire bond to the recess in the bond pad. The wire bond includes copper (Cu).Type: GrantFiled: November 2, 2023Date of Patent: October 8, 2024Assignee: NANYA TECHNOLOGY CORPORATIONInventors: Wei-Zhong Li, Yi-Ting Shih, Chien-Chung Wang, Hsih-Yang Chiu
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Publication number: 20240297166Abstract: An integrated circuit package and a method of forming the same are provided. The method includes attaching an integrated circuit die to a first substrate. A dummy die is formed. The dummy die is attached to the first substrate adjacent the integrated circuit die. An encapsulant is formed over the first substrate and surrounding the dummy die and the integrated circuit die. The encapsulant, the dummy die and the integrated circuit die are planarized, a topmost surface of the encapsulant being substantially level with a topmost surface of the dummy die and a topmost surface of the integrated circuit die. An interior portion of the dummy die is removed. A remaining portion of the dummy die forms an annular structure.Type: ApplicationFiled: May 15, 2024Publication date: September 5, 2024Inventors: Shang-Yun Hou, Sung-Hui Huang, Kuan-Yu Huang, Hsien-Pin Hu, Yushun Lin, Heh-Chang Huang, Hsing-Kuo Hsia, Chih-Chieh Hung, Ying-Ching Shih, Chin-Fu Kao, Wen-Hsin Wei, Li-Chung Kuo, Chi-Hsi Wu, Chen-Hua Yu
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Patent number: 12080617Abstract: A method for forming an underfill structure and semiconductor packages including the underfill structure are disclosed. In an embodiment, the semiconductor package may include a package including an integrated circuit die; an interposer bonded to the integrated circuit die by a plurality of die connectors; and an encapsulant surrounding the integrated circuit die. The semiconductor package may further include a package substrate bonded to the interposer by a plurality of conductive connectors; a first underfill between the package and the package substrate, the first underfill having a first coefficient of thermal expansion (CTE); and a second underfill surrounding the first underfill, the second underfill having a second CTE less than the first CTE.Type: GrantFiled: April 3, 2023Date of Patent: September 3, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Wei Chen, Li-Chung Kuo, Ying-Ching Shih, Szu-Wei Lu, Jing-Cheng Lin, Long Hua Lee, Kuan-Yu Huang