Patents by Inventor Chung Shin

Chung Shin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250114446
    Abstract: The present disclosure relates to a low glycosylated spike protein and a vaccine designed to express the spike protein in vivo. The present disclosure also teaches a method for generating an immune response by utilizing the low glycosylated spike protein, which provides a broader protection across different variants. A method for identifying a glycan-shielded conserved peptide of a glycoprotein is also disclosed.
    Type: Application
    Filed: October 8, 2024
    Publication date: April 10, 2025
    Inventors: Chung-Yi WU, Jeng-Shin LEE, Chi-Huey WONG
  • Patent number: 12241275
    Abstract: A seismically suspended isolation device is installed in a suspended configuration at a fixed end and comprises a first support module, a second support module, a first displacement suppressing module and a second displacement suppressing module. The first support module includes a first fixing element, a first moving element, and at least one first roller. The first roller is disposed between the first fixing element and the first moving element. The second support module includes a second fixing element, a second moving element, and at least one second roller. The second roller is disposed between the second fixing element and the second moving element. The first support module and the second support module are stacked together in an orthogonal manner, so that the seismically suspended isolation device generates motion in the first direction and the second direction when the seismically suspended isolation device subjected to an external force.
    Type: Grant
    Filed: November 24, 2023
    Date of Patent: March 4, 2025
    Assignee: NATIONAL APPLIED RESEARCH LABORATORIES
    Inventors: Chung-Han Yu, Shiang-Jung Wang, Kuo-Chun Chang, Jenn-Shin Hwang
  • Patent number: 12242789
    Abstract: Systems and methods disclosed are generally related to masklessly developing connections between a chip-group and a design connection point on a substrate. In placement of the chip-group on the substrate, according to certain embodiments the chip-group may be dispositioned relative to an expected position per a substrate layout design, causing a connection misalignment with the design connection point. According to certain embodiments, a machine learning (ML) model is trained on historical and simulated pixel models of chip-group connections and design connection points. Upon determining the chip-group misalignment by a metrology measurement, the trained ML model determines a pixel model to connect the misaligned chip-group, and causes the pixel model to be exposed to a substrate with a digital lithography tool, thereby connecting the dispositioned chip-group to the design connection point.
    Type: Grant
    Filed: February 12, 2024
    Date of Patent: March 4, 2025
    Assignee: Applied Materials, Inc.
    Inventors: Tamer Coskun, Aidyn Kemeldinov, Chung-Shin Kang, Uwe Hollerbach, Thomas L. Laidig
  • Publication number: 20250019989
    Abstract: A seismically suspended isolation device is installed in a suspended configuration at a fixed end and comprises a first support module, a second support module, a first displacement suppressing module and a second displacement suppressing module. The first support module includes a first fixing element, a first moving element, and at least one first roller. The first roller is disposed between the first fixing element and the first moving element. The second support module includes a second fixing element, a second moving element, and at least one second roller. The second roller is disposed between the second fixing element and the second moving element. The first support module and the second support module are stacked together in an orthogonal manner, so that the seismically suspended isolation device generates motion in the first direction and the second direction when the seismically suspended isolation device subjected to an external force.
    Type: Application
    Filed: November 24, 2023
    Publication date: January 16, 2025
    Inventors: Chung-Han YU, Shiang-Jung WANG, Kuo-Chun CHANG, Jenn-Shin HWANG
  • Publication number: 20240249062
    Abstract: Systems and methods disclosed are generally related to masklessly developing connections between a chip-group and a design connection point on a substrate. In placement of the chip-group on the substrate, according to certain embodiments the chip-group may be dispositioned relative to an expected position per a substrate layout design, causing a connection misalignment with the design connection point. According to certain embodiments, a machine learning (ML) model is trained on historical and simulated pixel models of chip-group connections and design connection points. Upon determining the chip-group misalignment by a metrology measurement, the trained ML model determines a pixel model to connect the misaligned chip-group, and causes the pixel model to be exposed to a substrate with a digital lithography tool, thereby connecting the dispositioned chip-group to the design connection point.
    Type: Application
    Filed: February 12, 2024
    Publication date: July 25, 2024
    Inventors: Tamer COSKUN, Aidyn KEMELDINOV, Chung-Shin KANG, Uwe HOLLERBACH, Thomas L. LAIDIG
  • Publication number: 20240152061
    Abstract: In embodiments of a digital lithography system, physical design data prepared at a data prep server in a hierarchical data structure. A leaf node comprises a repeater nod, comprising a bitmap image and a plurality of locations at which the bitmap appears in a physical design. At an EYE server, a repeater node bitmap is adjusted based upon, for example, spatial light modulator rotational adjustment and substrate distortion. The adjusted repeater node and the plurality of locations in which the adjusted repeater appears is compared to the repeater of the data prep server and its plurality of locations. In further embodiments, a rasterizer generates a checksum of bitmap to be printed to a substrate, from the EYE server bitmap. The checksum is compared to a checksum of the EYE server bitmap.
    Type: Application
    Filed: January 17, 2024
    Publication date: May 9, 2024
    Inventors: Chung-Shin KANG, Jun YANG, Hongbin JI
  • Publication number: 20240126180
    Abstract: Embodiments of the present disclosure relate to a system, a software application, and methods of digital lithography for semiconductor packaging. The method includes comparing positions of vias and via locations, generating position data based on the comparing the positions of vias and the via locations, providing the position data of the vias to a digital lithography device, updating a redistributed metal layer (RDL) mask pattern according to the position data such that RDL locations correspond to the positions of the vias, and projecting the RDL mask pattern with the digital lithography device.
    Type: Application
    Filed: October 10, 2023
    Publication date: April 18, 2024
    Inventors: Jang Fung CHEN, Thomas L. LAIDIG, Chung-Shin KANG, Chi-Ming TSAI, Wei-Ning SHEN
  • Patent number: 11934762
    Abstract: Systems and methods disclosed are generally related to masklessly developing connections between a chip-group and a design connection point on a substrate. In placement of the chip-group on the substrate, according to certain embodiments the chip-group may be dispositioned relative to an expected position per a substrate layout design, causing a connection misalignment with the design connection point. According to certain embodiments, a machine learning (ML) model is trained on historical and simulated pixel models of chip-group connections and design connection points. Upon determining the chip-group misalignment by a metrology measurement, the trained ML model determines a pixel model to connect the misaligned chip-group, and causes the pixel model to be exposed to a substrate with a digital lithography tool, thereby connecting the dispositioned chip-group to the design connection point.
    Type: Grant
    Filed: August 6, 2021
    Date of Patent: March 19, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Tamer Coskun, Aidyn Kemeldinov, Chung-Shin Kang, Uwe Hollerbach, Thomas L Laidig
  • Patent number: 11914305
    Abstract: In embodiments of a digital lithography system, physical design data prepared at a data prep server in a hierarchical data structure. A leaf node comprises a repeater nod, comprising a bitmap image and a plurality of locations at which the bitmap appears in a physical design. At an EYE server, a repeater node bitmap is adjusted based upon, for example, spatial light modulator rotational adjustment and substrate distortion. The adjusted repeater node and the plurality of locations in which the adjusted repeater appears is compared to the repeater of the data prep server and its plurality of locations. In further embodiments, a rasterizer generates a checksum of bitmap to be printed to a substrate, from the EYE server bitmap. The checksum is compared to a checksum of the EYE server bitmap.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: February 27, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Chung-Shin Kang, Jun Yang, Hongbin Ji
  • Patent number: 11906905
    Abstract: A verification device for verifying a design file for digital lithography comprises a memory and a controller. The memory comprises the design file. The controller is configured to access the design file and apply one or more compliance rules to the design file to determine compliance of the design file. The compliance rules comprises at least one of detecting non-orthogonal edges within the design file, detecting non-compliant overlapping structures within the design file, and detecting a non-compliant interaction between a reference layer of the design file and a target layer of the design file. The controller is further configured to verify the design file in response to a comparison of a number of non-orthogonal edges, non-compliant overlapping structures and non-compliant interactions to a threshold.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: February 20, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Chung-Shin Kang, Yinfeng Dong, Rick R. Hung, Yao Cheng Yang, Tsaichuan Kao
  • Publication number: 20230400895
    Abstract: A swappable device includes a first side cover, a lever, a sliding plate, a functional module interface card and a second side cover. When the lever is rotated to move a guide pillar of the lever to a lower end point of an arc-shaped guide groove of the first side cover, a guide pillar of the sliding plate moves toward a rear end point of a linear guide groove of the lever and a lower end point of a linear guide groove of the first side cover. The sliding plate is actuated to drive the functional module interface card to move toward a lower edge of the first side cover relative to the first side cover until a plurality of connectors of the functional module interface card are at the farthest position relative to an upper edge of the first side cover.
    Type: Application
    Filed: June 9, 2023
    Publication date: December 14, 2023
    Inventors: Shiang-Jiann LIU, Pin-Hsin KAO, Chung-Shin LIU
  • Publication number: 20230040198
    Abstract: Systems and methods disclosed are generally related to masklessly developing connections between a chip-group and a design connection point on a substrate. In placement of the chip-group on the substrate, according to certain embodiments the chip-group may be dispositioned relative to an expected position per a substrate layout design, causing a connection misalignment with the design connection point. According to certain embodiments, a machine learning (ML) model is trained on historical and simulated pixel models of chip-group connections and design connection points. Upon determining the chip-group misalignment by a metrology measurement, the trained ML model determines a pixel model to connect the misaligned chip-group, and causes the pixel model to be exposed to a substrate with a digital lithography tool, thereby connecting the dispositioned chip-group to the design connection point.
    Type: Application
    Filed: August 6, 2021
    Publication date: February 9, 2023
    Inventors: Tamer COSKUN, Aidyn KEMELDINOV, Chung-Shin KANG, Uwe HOLLERBACH, Thomas L. LAIDIG
  • Publication number: 20230042334
    Abstract: In embodiments of a digital lithography system, physical design data prepared at a data prep server in a hierarchical data structure. A leaf node comprises a repeater nod, comprising a bitmap image and a plurality of locations at which the bitmap appears in a physical design. At an EYE server, a repeater node bitmap is adjusted based upon, for example, spatial light modulator rotational adjustment and substrate distortion. The adjusted repeater node and the plurality of locations in which the adjusted repeater appears is compared to the repeater of the data prep server and its plurality of locations. In further embodiments, a rasterizer generates a checksum of bitmap to be printed to a substrate, from the EYE server bitmap. The checksum is compared to a checksum of the EYE server bitmap.
    Type: Application
    Filed: February 18, 2020
    Publication date: February 9, 2023
    Inventors: Chung-Shin KANG, Jun YANG, Hongbin JI
  • Publication number: 20220367438
    Abstract: A digital pattern generation system comprises a memory and a controller. The controller is coupled the memory and is configured to remove redundant cells from a digital pattern file, generate a first updated digital pattern file and compare the first updated digital pattern file with the digital pattern file. Further a number of vertexes of a first arc of the first updated digital pattern file is reduced to generate a second updated digital pattern file. Additionally, a first cell of the second updated digital pattern file is replaced with an alternative version of the first cell to generate a third updated digital pattern file. Further, one or more polygons within the third updated digital pattern file is converted to one or more quad polygons to generate an optimized digital pattern file.
    Type: Application
    Filed: September 23, 2019
    Publication date: November 17, 2022
    Inventors: Chung-Shin KANG, Thomas L. LAIDIG, Yinfeng DONG, Yao-Cheng YANG, Chen-Chien HUNG, Shivaraj Gururaj KAMALAPURA, Tsaichuan KAO
  • Publication number: 20220365443
    Abstract: A verification device for verifying a design file for digital lithography comprises a memory and a controller. The memory comprises the design file. The controller is configured to access the design file and apply one or more compliance rules to the design file to determine compliance of the design file. The compliance rules comprises at least one of detecting non-orthogonal edges within the design file, detecting non-compliant overlapping structures within the design file, and detecting a non-compliant interaction between a reference layer of the design file and a target layer of the design file. The controller is further configured to verify the design file in response to a comparison of a number of non-orthogonal edges, non-compliant overlapping structures and non-compliant interactions to a threshold.
    Type: Application
    Filed: November 15, 2019
    Publication date: November 17, 2022
    Inventors: Chung-Shin KANG, Yinfeng DONG, Rick R. HUNG, Yao Cheng YANG, Tsaichuan KAO
  • Patent number: 11058402
    Abstract: Provided is a heartbeat detection signal processing method of an ultrasonic Doppler fetus monitoring device that transmits an ultrasonic wave to the abdomen of a pregnant woman and detects a fetal heartbeat rate by receiving a Doppler variation signal generated according to the fetal heartbeat.
    Type: Grant
    Filed: December 23, 2015
    Date of Patent: July 13, 2021
    Assignee: BISTOS CO., LTD.
    Inventors: Chung Shin Kang, Seong Ill Ko
  • Publication number: 20190337554
    Abstract: An electric power steering system includes: a housing defining a receiving space therein; a worm shaft disposed in the receiving space to be engaged with a worm wheel; a tilt plug coupled to an inner surface of the housing to be fastened to a predetermined position, and coupled to the worm shaft which is inserted into the receiving space to support the worm shaft; and an elastic supporter which is installed to the housing to elastically support the tilt plug toward the worm wheel. The tilt plug is provided with a coupling protrusion which is protruded from an end portion of the tilt plug in a center axis of the tilt plug and slides into an inner surface of the housing, and the inner surface of the housing is provided with a coupling indentation into which the coupling protrusion slides to restrict rotation of the tilt plug.
    Type: Application
    Filed: October 20, 2017
    Publication date: November 7, 2019
    Applicant: ERAE AMS CO., LTD.
    Inventors: Se Jung PARK, Jung Rak SON, Chung Shin LEE
  • Patent number: 9321477
    Abstract: A rack bar support device supports a rack bar of a steering device of a vehicle toward a pinion shaft, and includes a rack bearing which is disposed opposite the pinion to contact the rack bar and a biasing assembly providing a force of pushing the rack bearing along a biasing axis toward the rack bar to urge the rack bearing to push the rack bar is engaged with the pinion shaft. The biasing assembly includes an adjustment plug, an adjustment assembly and a support plate assembly. The support plate assembly includes a support plate which is movably disposed between the adjustment member and the rack bearing in a state of being supported by the adjustment member, and a gap is formed between the support plate and the rack bearing.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: April 26, 2016
    Assignee: ERAE AUTOMOTIVE SYSTEMS CO., LTD.
    Inventors: Seong-Hun Bae, Chang-Wook Son, Chung-Shin Lee, Jin-Woong Lee, Je-Won Kim
  • Patent number: 9302249
    Abstract: A method for preparing composite sulfur-modified powdered activated carbon includes the following steps: providing a powdered activated carbon; proceeding a drying step on the powdered activated carbon; proceeding a liquid-phase sulfur modification step on the dried powdered activated carbon; proceeding a granulation step, so as to obtain a granular powdered activated carbon from the sulfur-modified powdered activated carbon; and proceeding a vapor-phase elemental sulfur heating step on the granular powdered activated carbon, so as to form the composite sulfur-modified powdered activated carbon.
    Type: Grant
    Filed: August 14, 2014
    Date of Patent: April 5, 2016
    Assignee: NATIONAL SUN YAT-SEN UNIVERSITY
    Inventors: Chung-Shin Yuan, Iau-Ren Ie, Huazhen Shen
  • Publication number: 20160081631
    Abstract: A respiratory waveform recognition method comprises: (a) detecting a respiratory airflow in a respiratory cycle; (b) measuring an amplitude of the respiratory airflow and a duration of the respiratory cycle; (c) using a plurality of sampling points to determine an inspiration waveform and an expiration waveform according to the amplitude and the duration; (d) normalizing the amplitude and the duration of one of the inspiration waveform and the expiration waveform, so as to establish a normalized waveform; and (e) accumulating the differences between the normalized waveform and a reference waveform to calculate a flow index useful for the identification of a normal respiration state and an abnormal respiration state. A curve, such as a weighted curve or a standard waveform, is used for fitting of the inspiration waveform or the expiration waveform to calculate the differences, and the differences are accumulated to identify the normal respiration state and the abnormal respiration state.
    Type: Application
    Filed: September 23, 2014
    Publication date: March 24, 2016
    Inventors: Kang-Ping LIN, Geng-Hong LIN, Hao-Yu JAN, Sheng-Cheng HUANG, Po-Chung SHIN, Ching-Liang YU, Da-Long LEE