Abstract: A method for forming a FinFET device structure is provided. The method includes forming a first fin structure and a second fin structure over a substrate and forming a liner layer over the first fin structure and the second fin structure. The method also includes forming an isolation layer over the liner layer and removing a portion of the liner layer and a portion of the isolation layer, such that the liner layer includes a first liner layer on an outer sidewall surface of the first fin structure and a second liner layer on an inner sidewall surface of the first fin structure, and a top surface of the second liner layer is higher than a top surface of the first liner layer.

Abstract: A method includes forming a fin on a substrate, forming an insulating material over the fin, recessing the insulating material to form an isolation region surrounding the fin, wherein an upper portion of the fin protrudes above the isolation region, performing a trimming process to reduce a width of the upper portion of the fin, and forming a gate structure extending over the isolation region and the upper portion of the fin.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate including a base and a fin structure over the base. The fin structure includes a nanostructure. The semiconductor device structure includes a gate stack over the base and wrapped around the nanostructure. The gate stack has an upper portion and a sidewall portion, the upper portion is over the nanostructure, and the sidewall portion is over a first sidewall of the nanostructure. The semiconductor device structure includes a first inner spacer and a second inner spacer over opposite sides of the sidewall portion. A sum of a first width of the first inner spacer and a second width of the second inner spacer is greater than a third width of the sidewall portion as measured along a longitudinal axis of the fin structure.

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes providing a semiconductor substrate. Alternating layers of a first semiconductor layer and a second semiconductor layer are formed. The first semiconductor layer is formed of a first semiconductor material, the second semiconductor layer formed of a second semiconductor material different from the first semiconductor material. The alternating layers of the first semiconductor layer and the second semiconductor layer are patterned to form stacks of the alternating layers and to expose lateral edges of the alternating layers in the stacks. Under etch conditions, the lateral edges of the alternating layers in the stacks are exposed to etchant to selectively etch recesses in the lateral edges of the first semiconductor layer such that a size of the recesses is substantially uniform.

Abstract: A method includes forming a fin on a substrate, forming an insulating material over the fin, recessing the insulating material to form an isolation region surrounding the fin, wherein an upper portion of the fin protrudes above the isolation region, performing a trimming process to reduce a width of the upper portion of the fin, and forming a gate structure extending over the isolation region and the upper portion of the fin.

Abstract: A method includes forming a fin on a substrate, forming an insulating material over the fin, recessing the insulating material to form an isolation region surrounding the fin, wherein an upper portion of the fin protrudes above the isolation region, performing a trimming process to reduce a width of the upper portion of the fin, and forming a gate structure extending over the isolation region and the upper portion of the fin.

Abstract: A method for forming a degreFinFET device structure is provided. The method includes forming a first fin structure and a second fin structure over a substrate and forming a liner layer over the first fin structure and the second fin structure. The method also includes forming an isolation layer over the liner layer and removing a portion of the liner layer and a portion of the isolation layer, such that the liner layer includes a first liner layer on an outer sidewall surface of the first fin structure and a second liner layer on an inner sidewall surface of the first fin structure, and a top surface of the second liner layer is higher than a top surface of the first liner layer.

Abstract: A method for forming a FinFET device structure is provided. The method includes forming a first fin structure and a second fin structure over a substrate and forming a liner layer over the first fin structure and the second fin structure. The method also includes forming an isolation layer over the liner layer and removing a portion of the liner layer and a portion of the isolation layer, such that the liner layer includes a first liner layer on an outer sidewall surface of the first fin structure and a second liner layer on an inner sidewall surface of the first fin structure, and a top surface of the second liner layer is higher than a top surface of the first liner layer.

Abstract: A method includes forming a fin on a substrate, forming an insulating material over the fin, recessing the insulating material to form an isolation region surrounding the fin, wherein an upper portion of the fin protrudes above the isolation region, performing a trimming process to reduce a width of the upper portion of the fin, and forming a gate structure extending over the isolation region and the upper portion of the fin.

Abstract: A method of forming a semiconductor device includes removing a top portion of a dielectric layer surrounding a metal gate to form a recess in the dielectric layer; filling the recess with a capping structure; forming a patterned hard mask over the capping structure and over the metal gate, wherein a portion of the metal gate, a portion of the capping structure, and a portion of the dielectric layer are aligned vertically with an opening of the patterned hard mask; and performing an etch process on said portions of the metal gate, the capping structure, and the dielectric layer that are aligned vertically with the opening of the patterned hard mask, wherein the capping structure has an etch resistance higher than an etch resistance of the dielectric layer during the etch process.

Abstract: A method includes forming a fin on a substrate, forming an insulating material over the fin, recessing the insulating material to form an isolation region surrounding the fin, wherein an upper portion of the fin protrudes above the isolation region, performing a trimming process to reduce a width of the upper portion of the fin, and forming a gate structure extending over the isolation region and the upper portion of the fin.

Abstract: A method of forming a semiconductor device includes removing a top portion of a dielectric layer surrounding a metal gate to form a recess in the dielectric layer; filling the recess with a capping structure; forming a patterned hard mask over the capping structure and over the metal gate, wherein a portion of the metal gate, a portion of the capping structure, and a portion of the dielectric layer are aligned vertically with an opening of the patterned hard mask; and performing an etch process on said portions of the metal gate, the capping structure, and the dielectric layer that are aligned vertically with the opening of the patterned hard mask, wherein the capping structure has an etch resistance higher than an etch resistance of the dielectric layer during the etch process.

Abstract: A method of forming a semiconductor structure includes forming a metal gate stack over a shallow trench isolation (STI) material in a semiconductor substrate, forming an interlayer dielectric over the STI material, recessing the interlayer dielectric to a height lower than a top surface of the metal gate stack, forming a helmet structure over the recessed interlayer dielectric, and after forming the helmet structure, etching the metal gate stack until reaching the STI material.

Abstract: A method for forming a FinFET device structure is provided. The method includes forming a first fin structure and a second fin structure over a substrate and forming a liner layer over the first fin structure and the second fin structure. The method also includes forming an isolation layer over the liner layer and removing a portion of the liner layer and a portion of the isolation layer, such that the liner layer includes a first liner layer on an outer sidewall surface of the first fin structure and a second liner layer on an inner sidewall surface of the first fin structure, and a top surface of the second liner layer is higher than a top surface of the first liner layer.

Abstract: A FinFET device structure and method for forming the same are provided. The FinFET device structure includes a first fin structure extending above a substrate, and the first fin structure includes a portion made of silicon germanium (SiGe). The FinFET device structure includes a second fin structure adjacent to the first fin structure. The FinFET device structure also includes a first liner layer formed on the outer sidewall surface of the first fin structure and a second liner layer formed on the inner sidewall surface of the first fin structure. The FinFET device structure further includes a first isolation structure formed on the substrate, and the first liner layer is between the first isolation structure and the first fin structure, and a top surface of the second liner layer is higher than a top surface of the first liner layer.

Abstract: A method of forming a semiconductor structure includes forming a metal gate stack over a shallow trench isolation (STI) material in a semiconductor substrate, forming an interlayer dielectric over the STI material, recessing the interlayer dielectric to a height lower than a top surface of the metal gate stack, forming a helmet structure over the recessed interlayer dielectric, and after forming the helmet structure, etching the metal gate stack until reaching the STI material.

Abstract: A method for forming a semiconductor device structure includes providing a substrate having a first fin structure and a second fin structure that are capped by a patterned hard mask structure. A liner layer and an overlying insulating layer are formed between the first and second fin structures. A multi-step etching process including a first step of selectively removing the patterned hard mask structure and a second step of in-situ and selectively removing a portion of the insulating layer to form an isolation feature is performed. The process gas used in the multi-step etching process includes a first etching gas and a second etching gas. The flow rate of the first etching gas is greater than that of the second etching gas in the first step and the flow rate of the first etching gas is less than that of the second etching gas in the second step.

Abstract: A FinFET device structure and method for forming the same are provided. The FinFET device structure includes a first fin structure extending above a substrate, and the first fin structure includes a portion made of silicon germanium (SiGe). The FinFET device structure includes a second fin structure adjacent to the first fin structure. The FinFET device structure also includes a first liner layer formed on the outer sidewall surface of the first fin structure and a second liner layer formed on the inner sidewall surface of the first fin structure. The FinFET device structure further includes a first isolation structure formed on the substrate, and the first liner layer is between the first isolation structure and the first fin structure, and a top surface of the second liner layer is higher than a top surface of the first liner layer.