Patents by Inventor Chung Sik Park

Chung Sik Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240120475
    Abstract: The present disclosure relates to a cathode active material for an all-solid-state battery with a controlled particle size and a method for preparing the same. In particular, the cathode active material includes lithium and a transition metal, wherein the cathode active material has a single peak in the range of 1 ?m to 10 ?m as a result of particle size distribution (PSD) analysis.
    Type: Application
    Filed: May 4, 2023
    Publication date: April 11, 2024
    Inventors: Sung Woo NOH, Hong Seok MIN, Sang Heon LEE, Jeong Hyun SEO, Im Sul SEO, Chung Bum LIM, Ju Yeong SEONG, Je Sik PARK
  • Patent number: 9942985
    Abstract: Disclosed is a printed circuit board including a base insulating layer, an upper insulating layer formed on the base insulating layer, a lower insulating layer formed under the base insulating layer. The upper insulating layer has a plurality of first vias filled in the first through holes, respectively, and the lower insulating layer has a second via filled in one second through hole formed through a top and a bottom surface and commonly connected with the first vias.
    Type: Grant
    Filed: February 20, 2015
    Date of Patent: April 10, 2018
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Seung Yul Shin, Jae Hwa Kim, Chung Sik Park, Chul Choi
  • Patent number: 9801275
    Abstract: A printed circuit board according to the embodiment includes an insulating layer; a first pad on a top surface of the insulating layer; a second pad on a bottom surface of the insulating layer; and a via formed in the insulating layer and having one surface connected to the first pad and an opposite surface connected to the second pad, wherein the via includes a plurality of via parts which are at least partially overlapped with each other.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: October 24, 2017
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Chung Sik Park, Jae Hwa Kim, Heun Gun Shin
  • Publication number: 20150245486
    Abstract: Disclosed is a printed circuit board including a base insulating layer, an upper insulating layer formed on the base insulating layer, a lower insulating layer formed under the base insulating layer. The upper insulating layer has a plurality of first vias filled in the first through holes, respectively, and the lower insulating layer has a second via filled in one second through hole formed through a top and a bottom surface and commonly connected with the first vias.
    Type: Application
    Filed: February 20, 2015
    Publication date: August 27, 2015
    Inventors: Seung Yul SHIN, Jae Hwa KIM, Chung Sik PARK, Chul CHOI
  • Publication number: 20150237728
    Abstract: A printed circuit board according to the embodiment includes an insulating layer; a first pad on a top surface of the insulating layer; a second pad on a bottom surface of the insulating layer; and a via formed in the insulating layer and having one surface connected to the first pad and an opposite surface connected to the second pad, wherein the via includes a plurality of via parts which are at least partially overlapped with each other.
    Type: Application
    Filed: February 13, 2015
    Publication date: August 20, 2015
    Inventors: Chung Sik PARK, Jae Hwa KIM, Heun Gun SHIN
  • Publication number: 20140060908
    Abstract: A printed circuit board includes a first insulating layer, a second insulating layer on the first insulating layer, and at least one via formed through the first and second insulating layers in a layered structure. The via includes a first via layer formed through the first insulating layer, a second via layer formed on the first via layer while passing through the second insulating layer, and an adhesive layer between the first and second via layers. The first via layer has a section different from a section of the second via layer. The adhesive property between the copper layer and the insulating layer is improved. The vias used to connect interlayer circuits to each other are formed between a plurality of insulating layers through an etching process instead of a laser process or a polishing process, thereby improving the process ability and reducing the manufacturing cost.
    Type: Application
    Filed: April 26, 2012
    Publication date: March 6, 2014
    Applicant: LG INNOTEK CO., LTD.
    Inventors: Chung Sik Park, Duk Nam Kim, Jae Hyun Ahn
  • Publication number: 20080279998
    Abstract: A toaster having at least one toasting slot includes at least one sensor operative to generate a sensor signal indicating whether or not a food item is loaded in said slot and heating elements for generating heat energy to toast a food item loaded in the toasting slot by use of an electrical current. The toaster also includes at least one switching unit that is responsive to the sensor signal and operative to control the electrical current flowing through the heating elements such that the switching unit cuts off the electrical current when the slot is unloaded.
    Type: Application
    Filed: May 9, 2007
    Publication date: November 13, 2008
    Inventor: Chung Sik Park