Abstract: A package structure including a semiconductor die, a redistribution layer structure and an electronic device is provided. The semiconductor die is laterally encapsulated by an insulating encapsulation. The redistribution layer structure is disposed on the semiconductor die and the insulating encapsulation. The redistribution layer structure includes a backside dielectric layer, inter-dielectric layers and redistribution conductive layers embedded in the backside dielectric layer and the inter-dielectric layers. The electronic device is disposed over the backside dielectric layer and electrically connected to an outermost redistribution conductive layer among the redistribution conductive layers, wherein the outermost redistribution conductive layer is embedded in the backside dielectric layer, and the backside dielectric layer comprises a ring-shaped recess covered by the outermost redistribution conductive layer.

Abstract: A package includes a frontside redistribution layer (RDL) structure, a semiconductor die on the frontside RDL structure, and a backside RDL structure on the semiconductor die including a first RDL, and a backside connector extending from a distal side of the first RDL and including a tapered portion having a width that decreases in a direction away from the first RDL, wherein the tapered portion includes a contact surface at an end of the tapered portion. A method of forming the package may include forming the backside redistribution layer (RDL) structure, attaching a semiconductor die to the backside RDL structure, forming an encapsulation layer around the semiconductor die on the backside RDL structure, and forming a frontside RDL structure on the semiconductor die and the encapsulation layer.

Abstract: An integrated fan-out package includes a first redistribution structure, a die, conductive structures, an encapsulant, and a second redistribution structure. The first redistribution structure has first regions and a second region surrounding the first regions. A metal density in the first regions is smaller than a metal density in the second region. The die is disposed over the first redistribution structure. The conductive structures are disposed on the first redistribution structure to surround the die. Vertical projections of the conductive structures onto the first redistribution structure fall within the first regions of the first redistribution structure. The encapsulant encapsulates the die and the conductive structures. The second redistribution structure is disposed on the encapsulant, the die, and the conductive structures.

Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.

Abstract: A bonded semiconductor structure includes a first device wafer and a second device wafer. The first device includes a first dielectric layer, a first bonding pad disposed in the first dielectric layer, and a first bonding layer on the first dielectric layer. The second device wafer includes a second dielectric layer, a second bonding layer on the second dielectric layer, and a second bonding pad disposed in the second dielectric layer and extending through the second bonding layer and at least a portion of the first bonding layer. A conductive bonding interface between the first bonding pad and the second bonding pad and a dielectric bonding interface between the first bonding layer and the second bonding layer include a step-height in a direction perpendicular to the dielectric bonding interface and the conductive bonding interface.

Abstract: An organic light-emitting diode (OLED) device includes a substrate, a well structure on the substrate with the well structure having a recess with side walls and a floor, a lower metal layer covering the floor and side-walls of the well, an upper conductive layer on the lower metal layer covering the floor of the well and contacting the lower metal layer, the upper conductive layer having outer edges at about an intersection of the side walls and the floor, a dielectric layer formed of an oxide of the lower metal layer covering the side walls of the well without covering the upper conductive layer, a stack of OLED layers covering at least the floor of the well, the upper conductive layer providing an electrode for the stack of OLED layers, and a light extraction layer (LEL) in the well over the stack of OLED layers and the dielectric layer.

Abstract: Exemplary subpixel structures include a directional light-emitting diode structure characterized by a full-width-half-maximum (FWHM) of emitted light having a divergence angle of less than or about 10°. The subpixel structure further includes a lens positioned a first distance from the light-emitting diode structure, where the lens is shaped to focus the emitted light from the light-emitting diode structure. The subpixel structure still further includes a patterned light absorption barrier positioned a second distance from the lens. The patterned light absorption barrier defines an opening in the barrier, and the focal point of the light focused by the lens is positioned within the opening. The subpixels structures may be incorporated into a pixel structure, and pixel structures may be incorporated into a display that is free of a polarizer layer.

Abstract: A light-emitting diode display including a substrate having a driving circuitry and a plurality of light emitting diode structures disposed on the substrate. Each light-emitting diode structure has a light emitting diode with a light emission zone having a planar portion, and a pigmentless light extraction layer of a UV-cured ink disposed over the light-emitting diode. The light extraction layer has a gradient in index of refraction along an axis normal to the planar portion, and the index of refraction of the light extraction layer decreases with distance from the planar portion.

Abstract: The present disclosure is generally related to 3D imaging capable OLED displays. A light field display comprises an array of 3D light field pixels, each of which comprises an array of corrugated OLED pixels, a metasurface layer disposed adjacent to the array of 3D light field pixels, and a plurality of median layers disposed between the metasurface layer and the corrugated OLED pixels. Each of the corrugated OLED pixels comprises primary or non-primary color subpixels, and produces a different view of an image through the median layers to the metasurface to form a 3D image. The corrugated OLED pixels combined with a cavity effect reduce a divergence of emitted light to enable effective beam direction manipulation by the metasurface. The metasurface having a higher refractive index and a smaller filling factor enables the deflection and direction of the emitted light from the corrugated OLED pixels to be well controlled.

Abstract: A method for forming a bonded semiconductor structure is disclosed. A first device wafer having a first bonding layer and a first bonding pad exposed from the first bonding layer and a second device wafer having a second bonding layer and a second bonding pad exposed from the second bonding layer are provided. Following, a portion of the first bonding pad is removed until a sidewall of the first bonding layer is exposed, and a portion of the second bonding layer is removed to expose a sidewall of the second bonding pad. The first device wafer and the second device wafer are then bonded to form a dielectric bonding interface between the first bonding layer and the second bonding layer and a conductive bonding interface between the first bonding pad and the second bonding pad. The conductive bonding interface and the dielectric bonding interface comprise a step-height.

Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.