Abstract: A process is implemented to form a contact opening in a semiconductor device that includes a gate electrode on a substrate, a spacer on a sidewall of the gate electrode and a dielectric material covering the gate electrode. The process comprises forming a photoresist pattern on a surface of the dielectric material, etching the dielectric material until the bottom liner layer is exposed, forming a protective layer on a sidewall of the spacer while etching the dielectric material, and etching the bottom liner layer.

Abstract: A passivation layer is deposited onto the surface of a substrate followed by deposition of a polymer layer, through the application of a plasma enhanced chemical vapor deposition process, in which the substrate is placed on a chuck within a reaction chamber and fluorocarbon gas is introduced into the reaction chamber under the influence of at least one plasma source. The fluorocarbon gas can be a CFX gas. The at least one plasma source can include a first plasma source that ionizes the fluorocarbon gas by applying RF plasma energy, and a second plasma source that applies a near-zero self-bias to the substrate at an RF frequency during deposition of the passivation layer and a greater bias during deposition of the polymer layer. The passivation layer is deposited prior to the polymer layer to protect the surface of the substrate from damage during the deposition of the polymer layer.

Abstract: A passivation layer is deposited onto the surface of a substrate followed by deposition of a polymer layer, through the application of a plasma enhanced chemical vapor deposition process, in which the substrate is placed on a chuck within a reaction chamber and fluorocarbon gas is introduced into the reaction chamber under the influence of at least one plasma source. The fluorocarbon gas can be a CFX gas. The at least one plasma source can include a first plasma source that ionizes the fluorocarbon gas by applying RF plasma energy, and a second plasma source that applies a near-zero self-bias to the substrate at an RF frequency during deposition of the passivation layer and a greater bias during deposition of the polymer layer. The passivation layer is deposited prior to the polymer layer to protect the surface of the substrate from damage during the deposition of the polymer layer.

Abstract: A semiconductor wafer cleaning method is provided. After cleaning the wafer with a chemical cleaning solution, the wafer is placed in a cleansing tank that fills with deionized water. A neutralizer is then added to the cleansing tank. The surface of the wafer is then neutralized to a neutral pH value. Thereafter, the chemical cleaning solution residue on the wafer surface is removed by cleaning the wafer with deionized water.

Abstract: First of all, a semiconductor substrate that has a memory array and a periphery region thereon is provided, wherein the memory array and the periphery region have a conducted layer, individually. Then an oxide layer or an oxide-nitride-oxide layer is formed on the conducted layer. Afterward, forming a photoresist layer on the oxide layer and defining the photoresist layer of the periphery region. The oxide layer and the conducted layer of the periphery region are etched until exposing the substrate surface of the periphery region by way of using a dry etching process and the photoresist layer as an etching mask. After the dry etching process is finished, a protected layer of the polymer will be formed on the etched sidewalls, so as to keep the etched profile. A wet etching process having a ultra dilute hydrofluoric acid (UDHF)or a mixed-acid solution SC1 is then performed to strip the protected layer of the polymer, so as to avoid the oxide loss.

Abstract: A cleaning method for semiconductor manufacturing process. A to-be-cleaned wafer having a metal layer thereon is provided. The wafer is placed into a chemical cleaning equipment unit to clean the wafer surface with a chemical cleaning solution while protecting the metal layer by a cathodic protection method. Next, the chemical cleaning solution on the wafer surface is rinsed away and the wafer is then dried to complete the cleaning method.

Abstract: A semiconductor wafer cleaning method is provided. A wafer is provided. The wafer is cleaned with a chemical cleaning solution, wherein the concentration of the chemical cleaning solution decreases as the cleaning time progresses. The wafer is then cleaned with deionized water to remove the chemical cleaning solution that is remained on the wafer surface.

Abstract: First of all, a semiconductor substrate with a memory array and a periphery region thereon is provided, wherein the memory array and the periphery region have a conducted layer, individually. Then an oxide-nitride-oxide layer is formed on the conducted layer. Afterward, forming a photoresist layer on the oxide layer and defining the photoresist layer of the periphery region is completed. The oxide layer and the conducted layer of the periphery region are etched by way of a dry etching process that uses the photoresist layer as an etching mask. A protected layer of the polymer will be formed on the etched sidewalls, so as to keep the etched profile. A wet etching process having a ultra dilite hydrofluoric acid (UDHF) or a mixed-acid solution (APM) is then performed to strip the protected layer of the polymer, so as to avoid any oxide loss.

Abstract: A semiconductor wafer cleaning method is provided. After cleaning the wafer with a chemical cleaning solution, the wafer is placed in a cleansing tank that fills with deionized water. A neutralizer is then added to the cleansing tank. The surface of the wafer is then neutralized to a neutral pH value. Thereafter, the chemical cleaning solution residue on the wafer surface is removed by cleaning the wafer with deionized water.

Abstract: A cleaning method for semiconductor manufacturing process. A to-be-cleaned wafer having a metal layer thereon is provided. The wafer is placed into a chemical cleaning equipment unit to clean the wafer surface with a chemical cleaning solution while protecting the metal layer by a cathodic protection method. Next, the chemical cleaning solution on the wafer surface is rinsed away and the wafer is then dried to complete the cleaning method.

Abstract: A fabrication method for a dual damascene structure is provided. A barrier layer and a copper seed layer are formed on a substrate comprising a dual damascene opening, wherein the barrier layer and the copper seed layer cover the dual damascene opening. A sacrificial layer is then formed on the copper seed layer, filling the dual damascene opening. Using the copper seed layer as an etch stop layer, the sacrificial layer is etch back. The exposed copper seed layer is then removed, followed by completely removing the sacrificial layer. A metal copper layer is formed in the dual damascene opening by plating, filling the opening of the dual damascene opening.