Patents by Inventor Chung-Tao Chen

Chung-Tao Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9577011
    Abstract: A fabricating method of CMOS transistor includes following steps. A first gate and a second gate are formed on a substrate. A gate insulator is formed on the substrate to cover the first and second gates. A first source, a first drain, a second source, and a second drain are formed on the gate insulator. The first source and the first drain are above the first gate. The second source and the second drain are above the second gate. A first channel layer and a mask layer are formed on the gate insulator. The mask layer is on the first channel layer. The first channel layer is above the first gate and contacts with the first source and the first drain. A second channel layer is formed on the gate insulator. The second channel layer is above the second gate and contacts with the second source and the second drain.
    Type: Grant
    Filed: May 26, 2015
    Date of Patent: February 21, 2017
    Assignee: Au Optronics Corporation
    Inventors: Chung-Tao Chen, Ta-Wei Chiu, Yu-Pu Lin, Yi-Wei Chen
  • Publication number: 20150255516
    Abstract: A fabricating method of CMOS transistor includes following steps. A first gate and a second gate are formed on a substrate. A gate insulator is formed on the substrate to cover the first and second gates. A first source, a first drain, a second source, and a second drain are formed on the gate insulator. The first source and the first drain are above the first gate. The second source and the second drain are above the second gate. A first channel layer and a mask layer are formed on the gate insulator. The mask layer is on the first channel layer. The first channel layer is above the first gate and contacts with the first source and the first drain. A second channel layer is formed on the gate insulator. The second channel layer is above the second gate and contacts with the second source and the second drain.
    Type: Application
    Filed: May 26, 2015
    Publication date: September 10, 2015
    Inventors: Chung-Tao Chen, Ta-Wei Chiu, Yu-Pu Lin, Yi-Wei Chen
  • Patent number: 9082792
    Abstract: A fabricating method of CMOS transistor includes following steps. A first gate and a second gate are formed on a substrate. A gate insulator is formed on the substrate to cover the first and second gates. A first source, a first drain, a second source, and a second drain are formed on the gate insulator. The first source and the first drain are above the first gate. The second source and the second drain are above the second gate. A first channel layer and a mask layer are formed on the gate insulator. The mask layer is on the first channel layer. The first channel layer is above the first gate and contacts with the first source and the first drain. A second channel layer is formed on the gate insulator. The second channel layer is above the second gate and contacts with the second source and the second drain.
    Type: Grant
    Filed: November 28, 2013
    Date of Patent: July 14, 2015
    Assignee: Au Optronics Corporation
    Inventors: Chung-Tao Chen, Ta-Wei Chiu, Yu-Pu Lin, Yi-Wei Chen
  • Patent number: 9012275
    Abstract: A method of forming TFT is provided. The TFT includes a gate electrode, a gate insulating layer, a first protective pattern, a second protective pattern, a source electrode, a drain electrode, a semiconductor channel layer, and a passivation layer. The first protective pattern and the second protective pattern are disposed on the gate insulating layer above the gate electrode. The source electrode is disposed on the gate insulating layer and the first protective pattern. The drain electrode is disposed on the gate insulating layer and the second protective pattern. The semiconductor channel layer is disposed on the gate insulating layer, the source electrode, and the drain electrode. In an extending direction from the source electrode to the drain electrode, a length of the first protective pattern is shorter than that of the source electrode, and a length of the second protective pattern is shorter than that of the drain electrode.
    Type: Grant
    Filed: December 2, 2013
    Date of Patent: April 21, 2015
    Assignee: AU Optronics Corp.
    Inventors: Chung-Tao Chen, Wu-Hsiung Lin, Po-Hsueh Chen
  • Patent number: 8829511
    Abstract: A hybrid thin film transistor includes a first thin film transistor and a second thin film transistor. The first thin film transistor includes a first gate, a first source, a first drain and a first semiconductor layer disposed between the first gate, the first source and the first drain, and the first semiconductor layer includes a crystallized silicon layer. The second thin film transistor includes a second gate, a second source, a second drain and a second semiconductor layer disposed between the second gate, the second source and the second drain, and the second semiconductor layer includes a metal oxide semiconductor layer.
    Type: Grant
    Filed: September 15, 2011
    Date of Patent: September 9, 2014
    Assignee: Au Optronics Corporation
    Inventors: Hsiu-Chun Hsieh, Yi-Wei Chen, Ta-Wei Chiu, Chung-Tao Chen
  • Patent number: 8766270
    Abstract: A pixel structure is provided. A first insulating pattern is on the first polysilicon pattern. A second insulating pattern is on the second polysilicon pattern and separated from the first insulating pattern. An insulating layer covers the first and the second insulating patterns. A first gate and a second gate are on the insulating layer. A first covering layer covers the first and the second gates. A first source metal layer and a first drain metal layer are on the first covering layer and electrically connected to a first source region and a first drain region. A second source metal layer and a second drain metal layer are on the first covering layer and electrically connected to a second source region and a second drain region. A pixel electrode is electrically connected to the first drain metal layer.
    Type: Grant
    Filed: January 11, 2011
    Date of Patent: July 1, 2014
    Assignee: Au Optronics Corporation
    Inventors: Hsiu-Chun Hsieh, Yi-Wei Chen, Ta-Wei Chiu, Chung-Tao Chen
  • Publication number: 20140087525
    Abstract: A fabricating method of CMOS transistor includes following steps. A first gate and a second gate are formed on a substrate. A gate insulator is formed on the substrate to cover the first and second gates. A first source, a first drain, a second source, and a second drain are formed on the gate insulator. The first source and the first drain are above the first gate. The second source and the second drain are above the second gate. A first channel layer and a mask layer are formed on the gate insulator. The mask layer is on the first channel layer. The first channel layer is above the first gate and contacts with the first source and the first drain. A second channel layer is formed on the gate insulator. The second channel layer is above the second gate and contacts with the second source and the second drain.
    Type: Application
    Filed: November 28, 2013
    Publication date: March 27, 2014
    Applicant: Au Optronics Corporation
    Inventors: Chung-Tao Chen, Ta-Wei Chiu, Yu-Pu Lin, Yi-Wei Chen
  • Publication number: 20140080271
    Abstract: A method of forming TFT is provided. The TFT includes a gate electrode, a gate insulating layer, a first protective pattern, a second protective pattern, a source electrode, a drain electrode, a semiconductor channel layer, and a passivation layer. The first protective pattern and the second protective pattern are disposed on the gate insulating layer above the gate electrode. The source electrode is disposed on the gate insulating layer and the first protective pattern. The drain electrode is disposed on the gate insulating layer and the second protective pattern. The semiconductor channel layer is disposed on the gate insulating layer, the source electrode, and the drain electrode. In an extending direction from the source electrode to the drain electrode, a length of the first protective pattern is shorter than that of the source electrode, and a length of the second protective pattern is shorter than that of the drain electrode.
    Type: Application
    Filed: December 2, 2013
    Publication date: March 20, 2014
    Applicant: AU Optronics Corp.
    Inventors: Chung-Tao Chen, Wu-Hsiung Lin, Po-Hsueh Chen
  • Patent number: 8674350
    Abstract: A thin film transistor (TFT) includes a gate electrode, a gate insulating layer, a first protective pattern, a second protective pattern, a source electrode, a drain electrode, a semiconductor channel layer, and a passivation layer. The first protective pattern and the second protective pattern are disposed on the gate insulating layer above the gate electrode. The source electrode is disposed on the gate insulating layer and the first protective pattern. The drain electrode is disposed on the gate insulating layer and the second protective pattern. The semiconductor channel layer is disposed on the gate insulating layer, the source electrode, and the drain electrode. In an extending direction from the source electrode to the drain electrode, a length of the first protective pattern is shorter than that of the source electrode, and a length of the second protective pattern is shorter than that of the drain electrode.
    Type: Grant
    Filed: October 30, 2011
    Date of Patent: March 18, 2014
    Assignee: AU Optronics Corp.
    Inventors: Chung-Tao Chen, Wu-Hsiung Lin, Po-Hsueh Chen
  • Patent number: 8659092
    Abstract: A fabricating method of CMOS transistor includes following steps. A first gate and a second gate are formed on a substrate. A gate insulator is formed on the substrate to cover the first and second gates. A first source, a first drain, a second source, and a second drain are formed on the gate insulator. The first source and the first drain are above the first gate. The second source and the second drain are above the second gate. A first channel layer and a mask layer are formed on the gate insulator. The mask layer is on the first channel layer. The first channel layer is above the first gate and contacts with the first source and the first drain. A second channel layer is formed on the gate insulator. The second channel layer is above the second gate and contacts with the second source and the second drain.
    Type: Grant
    Filed: November 10, 2010
    Date of Patent: February 25, 2014
    Assignee: Au Optronics Corporation
    Inventors: Chung-Tao Chen, Ta-Wei Chiu, Yu-Pu Lin, Yi-Wei Chen
  • Publication number: 20130049002
    Abstract: A thin film transistor (TFT) includes a gate electrode, a gate insulating layer, a first protective pattern, a second protective pattern, a source electrode, a drain electrode, a semiconductor channel layer, and a passivation layer. The first protective pattern and the second protective pattern are disposed on the gate insulating layer above the gate electrode. The source electrode is disposed on the gate insulating layer and the first protective pattern. The drain electrode is disposed on the gate insulating layer and the second protective pattern. The semiconductor channel layer is disposed on the gate insulating layer, the source electrode, and the drain electrode. In an extending direction from the source electrode to the drain electrode, a length of the first protective pattern is shorter than that of the source electrode, and a length of the second protective pattern is shorter than that of the drain electrode.
    Type: Application
    Filed: October 30, 2011
    Publication date: February 28, 2013
    Inventors: Chung-Tao Chen, Wu-Hsiung Lin, Po-Hsueh Chen
  • Publication number: 20120305910
    Abstract: A hybrid thin film transistor includes a first thin film transistor and a second thin film transistor. The first thin film transistor includes a first gate, a first source, a first drain and a first semiconductor layer disposed between the first gate, the first source and the first drain, and the first semiconductor layer includes a crystallized silicon layer. The second thin film transistor includes a second gate, a second source, a second drain and a second semiconductor layer disposed between the second gate, the second source and the second drain, and the second semiconductor layer includes a metal oxide semiconductor layer.
    Type: Application
    Filed: September 15, 2011
    Publication date: December 6, 2012
    Applicant: AU OPTRONICS CORPORATION
    Inventors: Hsiu-Chun Hsieh, Yi-Wei Chen, Ta-Wei Chiu, Chung-Tao Chen
  • Publication number: 20120049197
    Abstract: A pixel structure is provided. A first insulating pattern is on the first polysilicon pattern. A second insulating pattern is on the second polysilicon pattern and separated from the first insulating pattern. An insulating layer covers the first and the second insulating patterns. A first gate and a second gate are on the insulating layer. A first covering layer covers the first and the second gates. A first source metal layer and a first drain metal layer are on the first covering layer and electrically connected to a first source region and a first drain region. A second source metal layer and a second drain metal layer are on the first covering layer and electrically connected to a second source region and a second drain region. A pixel electrode is electrically connected to the first drain metal layer.
    Type: Application
    Filed: January 11, 2011
    Publication date: March 1, 2012
    Applicant: AU OPTRONICS CORPORATION
    Inventors: Hsiu-Chun Hsieh, Yi-Wei Chen, Ta-Wei Chiu, Chung-Tao Chen
  • Publication number: 20120025320
    Abstract: A fabricating method of CMOS transistor includes following steps. A first gate and a second gate are formed on a substrate. A gate insulator is formed on the substrate to cover the first and second gates. A first source, a first drain, a second source, and a second drain are formed on the gate insulator. The first source and the first drain are above the first gate. The second source and the second drain are above the second gate. A first channel layer and a mask layer are formed on the gate insulator. The mask layer is on the first channel layer. The first channel layer is above the first gate and contacts with the first source and the first drain. A second channel layer is formed on the gate insulator. The second channel layer is above the second gate and contacts with the second source and the second drain.
    Type: Application
    Filed: November 10, 2010
    Publication date: February 2, 2012
    Applicant: AU OPTRONICS CORPORATION
    Inventors: Chung-Tao Chen, Ta-Wei Chiu, Yu-Pu Lin, Yi-Wei Chen