Patents by Inventor Chung-Tao Chen
Chung-Tao Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9577011Abstract: A fabricating method of CMOS transistor includes following steps. A first gate and a second gate are formed on a substrate. A gate insulator is formed on the substrate to cover the first and second gates. A first source, a first drain, a second source, and a second drain are formed on the gate insulator. The first source and the first drain are above the first gate. The second source and the second drain are above the second gate. A first channel layer and a mask layer are formed on the gate insulator. The mask layer is on the first channel layer. The first channel layer is above the first gate and contacts with the first source and the first drain. A second channel layer is formed on the gate insulator. The second channel layer is above the second gate and contacts with the second source and the second drain.Type: GrantFiled: May 26, 2015Date of Patent: February 21, 2017Assignee: Au Optronics CorporationInventors: Chung-Tao Chen, Ta-Wei Chiu, Yu-Pu Lin, Yi-Wei Chen
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Publication number: 20150255516Abstract: A fabricating method of CMOS transistor includes following steps. A first gate and a second gate are formed on a substrate. A gate insulator is formed on the substrate to cover the first and second gates. A first source, a first drain, a second source, and a second drain are formed on the gate insulator. The first source and the first drain are above the first gate. The second source and the second drain are above the second gate. A first channel layer and a mask layer are formed on the gate insulator. The mask layer is on the first channel layer. The first channel layer is above the first gate and contacts with the first source and the first drain. A second channel layer is formed on the gate insulator. The second channel layer is above the second gate and contacts with the second source and the second drain.Type: ApplicationFiled: May 26, 2015Publication date: September 10, 2015Inventors: Chung-Tao Chen, Ta-Wei Chiu, Yu-Pu Lin, Yi-Wei Chen
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Patent number: 9082792Abstract: A fabricating method of CMOS transistor includes following steps. A first gate and a second gate are formed on a substrate. A gate insulator is formed on the substrate to cover the first and second gates. A first source, a first drain, a second source, and a second drain are formed on the gate insulator. The first source and the first drain are above the first gate. The second source and the second drain are above the second gate. A first channel layer and a mask layer are formed on the gate insulator. The mask layer is on the first channel layer. The first channel layer is above the first gate and contacts with the first source and the first drain. A second channel layer is formed on the gate insulator. The second channel layer is above the second gate and contacts with the second source and the second drain.Type: GrantFiled: November 28, 2013Date of Patent: July 14, 2015Assignee: Au Optronics CorporationInventors: Chung-Tao Chen, Ta-Wei Chiu, Yu-Pu Lin, Yi-Wei Chen
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Patent number: 9012275Abstract: A method of forming TFT is provided. The TFT includes a gate electrode, a gate insulating layer, a first protective pattern, a second protective pattern, a source electrode, a drain electrode, a semiconductor channel layer, and a passivation layer. The first protective pattern and the second protective pattern are disposed on the gate insulating layer above the gate electrode. The source electrode is disposed on the gate insulating layer and the first protective pattern. The drain electrode is disposed on the gate insulating layer and the second protective pattern. The semiconductor channel layer is disposed on the gate insulating layer, the source electrode, and the drain electrode. In an extending direction from the source electrode to the drain electrode, a length of the first protective pattern is shorter than that of the source electrode, and a length of the second protective pattern is shorter than that of the drain electrode.Type: GrantFiled: December 2, 2013Date of Patent: April 21, 2015Assignee: AU Optronics Corp.Inventors: Chung-Tao Chen, Wu-Hsiung Lin, Po-Hsueh Chen
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Patent number: 8829511Abstract: A hybrid thin film transistor includes a first thin film transistor and a second thin film transistor. The first thin film transistor includes a first gate, a first source, a first drain and a first semiconductor layer disposed between the first gate, the first source and the first drain, and the first semiconductor layer includes a crystallized silicon layer. The second thin film transistor includes a second gate, a second source, a second drain and a second semiconductor layer disposed between the second gate, the second source and the second drain, and the second semiconductor layer includes a metal oxide semiconductor layer.Type: GrantFiled: September 15, 2011Date of Patent: September 9, 2014Assignee: Au Optronics CorporationInventors: Hsiu-Chun Hsieh, Yi-Wei Chen, Ta-Wei Chiu, Chung-Tao Chen
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Patent number: 8766270Abstract: A pixel structure is provided. A first insulating pattern is on the first polysilicon pattern. A second insulating pattern is on the second polysilicon pattern and separated from the first insulating pattern. An insulating layer covers the first and the second insulating patterns. A first gate and a second gate are on the insulating layer. A first covering layer covers the first and the second gates. A first source metal layer and a first drain metal layer are on the first covering layer and electrically connected to a first source region and a first drain region. A second source metal layer and a second drain metal layer are on the first covering layer and electrically connected to a second source region and a second drain region. A pixel electrode is electrically connected to the first drain metal layer.Type: GrantFiled: January 11, 2011Date of Patent: July 1, 2014Assignee: Au Optronics CorporationInventors: Hsiu-Chun Hsieh, Yi-Wei Chen, Ta-Wei Chiu, Chung-Tao Chen
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Publication number: 20140087525Abstract: A fabricating method of CMOS transistor includes following steps. A first gate and a second gate are formed on a substrate. A gate insulator is formed on the substrate to cover the first and second gates. A first source, a first drain, a second source, and a second drain are formed on the gate insulator. The first source and the first drain are above the first gate. The second source and the second drain are above the second gate. A first channel layer and a mask layer are formed on the gate insulator. The mask layer is on the first channel layer. The first channel layer is above the first gate and contacts with the first source and the first drain. A second channel layer is formed on the gate insulator. The second channel layer is above the second gate and contacts with the second source and the second drain.Type: ApplicationFiled: November 28, 2013Publication date: March 27, 2014Applicant: Au Optronics CorporationInventors: Chung-Tao Chen, Ta-Wei Chiu, Yu-Pu Lin, Yi-Wei Chen
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Publication number: 20140080271Abstract: A method of forming TFT is provided. The TFT includes a gate electrode, a gate insulating layer, a first protective pattern, a second protective pattern, a source electrode, a drain electrode, a semiconductor channel layer, and a passivation layer. The first protective pattern and the second protective pattern are disposed on the gate insulating layer above the gate electrode. The source electrode is disposed on the gate insulating layer and the first protective pattern. The drain electrode is disposed on the gate insulating layer and the second protective pattern. The semiconductor channel layer is disposed on the gate insulating layer, the source electrode, and the drain electrode. In an extending direction from the source electrode to the drain electrode, a length of the first protective pattern is shorter than that of the source electrode, and a length of the second protective pattern is shorter than that of the drain electrode.Type: ApplicationFiled: December 2, 2013Publication date: March 20, 2014Applicant: AU Optronics Corp.Inventors: Chung-Tao Chen, Wu-Hsiung Lin, Po-Hsueh Chen
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Patent number: 8674350Abstract: A thin film transistor (TFT) includes a gate electrode, a gate insulating layer, a first protective pattern, a second protective pattern, a source electrode, a drain electrode, a semiconductor channel layer, and a passivation layer. The first protective pattern and the second protective pattern are disposed on the gate insulating layer above the gate electrode. The source electrode is disposed on the gate insulating layer and the first protective pattern. The drain electrode is disposed on the gate insulating layer and the second protective pattern. The semiconductor channel layer is disposed on the gate insulating layer, the source electrode, and the drain electrode. In an extending direction from the source electrode to the drain electrode, a length of the first protective pattern is shorter than that of the source electrode, and a length of the second protective pattern is shorter than that of the drain electrode.Type: GrantFiled: October 30, 2011Date of Patent: March 18, 2014Assignee: AU Optronics Corp.Inventors: Chung-Tao Chen, Wu-Hsiung Lin, Po-Hsueh Chen
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Patent number: 8659092Abstract: A fabricating method of CMOS transistor includes following steps. A first gate and a second gate are formed on a substrate. A gate insulator is formed on the substrate to cover the first and second gates. A first source, a first drain, a second source, and a second drain are formed on the gate insulator. The first source and the first drain are above the first gate. The second source and the second drain are above the second gate. A first channel layer and a mask layer are formed on the gate insulator. The mask layer is on the first channel layer. The first channel layer is above the first gate and contacts with the first source and the first drain. A second channel layer is formed on the gate insulator. The second channel layer is above the second gate and contacts with the second source and the second drain.Type: GrantFiled: November 10, 2010Date of Patent: February 25, 2014Assignee: Au Optronics CorporationInventors: Chung-Tao Chen, Ta-Wei Chiu, Yu-Pu Lin, Yi-Wei Chen
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Publication number: 20130049002Abstract: A thin film transistor (TFT) includes a gate electrode, a gate insulating layer, a first protective pattern, a second protective pattern, a source electrode, a drain electrode, a semiconductor channel layer, and a passivation layer. The first protective pattern and the second protective pattern are disposed on the gate insulating layer above the gate electrode. The source electrode is disposed on the gate insulating layer and the first protective pattern. The drain electrode is disposed on the gate insulating layer and the second protective pattern. The semiconductor channel layer is disposed on the gate insulating layer, the source electrode, and the drain electrode. In an extending direction from the source electrode to the drain electrode, a length of the first protective pattern is shorter than that of the source electrode, and a length of the second protective pattern is shorter than that of the drain electrode.Type: ApplicationFiled: October 30, 2011Publication date: February 28, 2013Inventors: Chung-Tao Chen, Wu-Hsiung Lin, Po-Hsueh Chen
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Publication number: 20120305910Abstract: A hybrid thin film transistor includes a first thin film transistor and a second thin film transistor. The first thin film transistor includes a first gate, a first source, a first drain and a first semiconductor layer disposed between the first gate, the first source and the first drain, and the first semiconductor layer includes a crystallized silicon layer. The second thin film transistor includes a second gate, a second source, a second drain and a second semiconductor layer disposed between the second gate, the second source and the second drain, and the second semiconductor layer includes a metal oxide semiconductor layer.Type: ApplicationFiled: September 15, 2011Publication date: December 6, 2012Applicant: AU OPTRONICS CORPORATIONInventors: Hsiu-Chun Hsieh, Yi-Wei Chen, Ta-Wei Chiu, Chung-Tao Chen
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Publication number: 20120049197Abstract: A pixel structure is provided. A first insulating pattern is on the first polysilicon pattern. A second insulating pattern is on the second polysilicon pattern and separated from the first insulating pattern. An insulating layer covers the first and the second insulating patterns. A first gate and a second gate are on the insulating layer. A first covering layer covers the first and the second gates. A first source metal layer and a first drain metal layer are on the first covering layer and electrically connected to a first source region and a first drain region. A second source metal layer and a second drain metal layer are on the first covering layer and electrically connected to a second source region and a second drain region. A pixel electrode is electrically connected to the first drain metal layer.Type: ApplicationFiled: January 11, 2011Publication date: March 1, 2012Applicant: AU OPTRONICS CORPORATIONInventors: Hsiu-Chun Hsieh, Yi-Wei Chen, Ta-Wei Chiu, Chung-Tao Chen
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Publication number: 20120025320Abstract: A fabricating method of CMOS transistor includes following steps. A first gate and a second gate are formed on a substrate. A gate insulator is formed on the substrate to cover the first and second gates. A first source, a first drain, a second source, and a second drain are formed on the gate insulator. The first source and the first drain are above the first gate. The second source and the second drain are above the second gate. A first channel layer and a mask layer are formed on the gate insulator. The mask layer is on the first channel layer. The first channel layer is above the first gate and contacts with the first source and the first drain. A second channel layer is formed on the gate insulator. The second channel layer is above the second gate and contacts with the second source and the second drain.Type: ApplicationFiled: November 10, 2010Publication date: February 2, 2012Applicant: AU OPTRONICS CORPORATIONInventors: Chung-Tao Chen, Ta-Wei Chiu, Yu-Pu Lin, Yi-Wei Chen