Patents by Inventor Chung-Ting Ko

Chung-Ting Ko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12272553
    Abstract: A method includes forming an etching mask, which includes forming a bottom anti-reflective coating over a target layer, forming an inorganic middle layer over the bottom anti-reflective coating, and forming a patterned photo resist over the inorganic middle layer. The patterns of the patterned photo resist are transferred into the inorganic middle layer and the bottom anti-reflective coating to form a patterned inorganic middle layer and a patterned bottom anti-reflective coating, respectively. The patterned inorganic middle layer is then removed. The target layer is etched using the patterned bottom anti-reflective coating to define a pattern in the target layer.
    Type: Grant
    Filed: July 25, 2023
    Date of Patent: April 8, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Ting Ko, Tai-Chun Huang, Chi On Chui
  • Publication number: 20250087529
    Abstract: A method for filling a gap includes: filling a dielectric layer in the gap so that a seam is formed in the dielectric layer, the dielectric layer including two surface portions at two opposite sides of the seam, respectively; introducing a surface modification agent into the seam such that each of the two surface portions has first functional groups and second functional groups; forming a stress layer on the dielectric layer to cover the seam, the stress layer including a material different from that of the dielectric layer; and applying an energy field to permit the two surface portions to bond with each other through reaction between the first functional groups and the second functional groups.
    Type: Application
    Filed: September 11, 2023
    Publication date: March 13, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Hsien CHENG, Tai-Chun HUANG, Chung-Ting KO, Chia-Yu FANG, Sung-En LIN, Yu-Yun PENG
  • Publication number: 20250081507
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a source/drain (S/D) feature disposed over a substrate and between two adjacent semiconductor layers, an inner spacer disposed between and in contact with one semiconductor layer and the substrate, and a dielectric layer structure disposed between the S/D feature and the substrate. The dielectric layer structure includes a first dielectric layer in contact with the inner spacer and the substrate, and a second dielectric layer nested within the first dielectric layer, wherein a bottom surface and sidewall surfaces of the second dielectric layer are in contact with the first dielectric layer.
    Type: Application
    Filed: January 4, 2024
    Publication date: March 6, 2025
    Inventors: Ting-Hsiang CHANG, Chung-Ting KO, Shu Ling LIAO, Sung-En LIN
  • Publication number: 20250081529
    Abstract: Embodiments with present disclosure provides a gate-all-around FET device including extended bottom inner spacers. The extended bottom inner prevents the subsequently formed epitaxial source/drain region from volume loss and induces compressive strain in the channel region to prevent strain loss and channel resistance degradation.
    Type: Application
    Filed: March 1, 2024
    Publication date: March 6, 2025
    Inventors: Chien-Chia CHENG, Chih-Chiang CHANG, Ming-Hua YU, Chii-Horng LI, Chung-Ting KO, Sung-En LIN, Chih-Shan CHEN, De-Fang CHEN
  • Patent number: 12237393
    Abstract: A semiconductor device including a gate structure disposed on a substrate is provided. The gate structure includes a work function setting layer and a work function tuning layer sequentially disposed on substrate. The work function tuning layer is in contact with an interface surface positioned between the work function setting layer and the work function tuning layer, and a material of the interface surface is different from the work function setting layer.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: February 25, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Ting Ko, Bi-Fen Wu, Chi-On Chui
  • Publication number: 20250056851
    Abstract: A semiconductor device includes a first channel region, a second channel region, and a first insulating fin, the first insulating fin being interposed between the first channel region and the second channel region. The first insulating fin includes a lower portion and an upper portion. The lower portion includes a fill material. The upper portion includes a first dielectric layer on the lower portion, the first dielectric layer being a first dielectric material, a first capping layer on the first dielectric layer, the first capping layer being a second dielectric material, the second dielectric material being different than the first dielectric material, and a second dielectric layer on the first capping layer, the second dielectric layer being the first dielectric material.
    Type: Application
    Filed: October 28, 2024
    Publication date: February 13, 2025
    Inventors: Jen-Hong Chang, Yi-Hsiu Liu, You-Ting Lin, Chih-Chung Chang, Kuo-Yi Chao, Jiun-Ming Kuo, Yuan-Ching Peng, Sung-En Lin, Chia-Cheng Chao, Chung-Ting Ko
  • Publication number: 20250048711
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a source/drain (S/D) feature disposed in a recess between two adjacent channel regions, wherein the S/D feature comprises an epitaxial layer conformally deposited on an exposed surface of the recess. The structure also includes a silicide layer conformally disposed on the S/D feature, and a S/D contact disposed on the silicide layer, wherein the S/D contact has a first portion extending into the recess, and the first portion has at least three surfaces being surrounded by the silicide layer and the S/D feature.
    Type: Application
    Filed: December 4, 2023
    Publication date: February 6, 2025
    Inventors: Chung-Ting KO, Shu Ling LIAO, Sung-En LIN
  • Patent number: 12218241
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a gate structure over the substrate. The semiconductor device structure also includes a spacer element covering a first sidewall of the gate structure. The semiconductor device structure further includes a source/drain portion in the substrate, and the spacer element is between the source/drain portion and the gate structure. In addition, the semiconductor device structure includes an etch stop layer covering the source/drain portion. The etch stop layer includes a first nitride layer covering the source/drain portion and having a second sidewall, and the second sidewall is in direct contact with the spacer element. The etch stop layer also includes a first silicon layer covering the first nitride layer and having a third sidewall, and the third sidewall is in direct contact with the spacer element.
    Type: Grant
    Filed: March 28, 2022
    Date of Patent: February 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Ting Ko, Bo-Cyuan Lu, Jr-Hung Li, Chi-On Chui
  • Publication number: 20240429313
    Abstract: A method includes etching a semiconductor region aside of a gate stack to form a recess, forming a dielectric layer at a bottom of the recess, selectively forming a first semiconductor layer at the bottom of the recess, and epitaxially growing a second semiconductor layer on the first semiconductor layer. A bottom surface of the first semiconductor layer forms an interface with a top surface of the dielectric layer, with the interface extending to opposing sides of the recess. The selectively forming the first semiconductor layer comprises a first deposition process performed under first process conditions. The second semiconductor layer is formed using a second deposition process under second process conditions. The second process conditions are different from the first process conditions.
    Type: Application
    Filed: September 28, 2023
    Publication date: December 26, 2024
    Inventors: Yu-Cheng Shiau, Chung-Ting Ko, Ting-Hsiang Chang, Shu Ling Liao, Sung-En Lin, Tai-Chun Huang, Tze-Liang Lee
  • Publication number: 20240413157
    Abstract: Improved methods for forming gate isolation structures between portions of gate electrodes and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes forming a channel structure over a substrate; forming a first isolation structure extending in a direction parallel to the channel structure; forming a dummy gate structure over the channel structure and the first isolation structure; depositing a hard mask layer over the dummy gate structure; etching the hard mask layer to form a first opening through the hard mask layer over the first isolation structure; conformally depositing a first dielectric layer over the hard mask layer, in the first opening, and over the dummy gate structure; etching the first dielectric layer to extend the first opening and expose the dummy gate structure; and etching the dummy gate structure to extend the first opening and expose the first isolation structure.
    Type: Application
    Filed: June 13, 2024
    Publication date: December 12, 2024
    Inventors: Li-Fong Lin, Wan Chen Hsieh, Chung-Ting Ko, Tai-Chun Huang
  • Patent number: 12166076
    Abstract: A semiconductor device includes a first channel region, a second channel region, and a first insulating fin, the first insulating fin being interposed between the first channel region and the second channel region. The first insulating fin includes a lower portion and an upper portion. The lower portion includes a fill material. The upper portion includes a first dielectric layer on the lower portion, the first dielectric layer being a first dielectric material, a first capping layer on the first dielectric layer, the first capping layer being a second dielectric material, the second dielectric material being different than the first dielectric material, and a second dielectric layer on the first capping layer, the second dielectric layer being the first dielectric material.
    Type: Grant
    Filed: August 16, 2021
    Date of Patent: December 10, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jen-Hong Chang, Yi-Hsiu Liu, You-Ting Lin, Chih-Chung Chang, Kuo-Yi Chao, Jiun-Ming Kuo, Yuan-Ching Peng, Sung-En Lin, Chia-Cheng Chao, Chung-Ting Ko
  • Patent number: 12166035
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes an isolation structure formed over a semiconductor substrate. A first fin structure and a second fin structure extend from the semiconductor substrate and protrude above the isolation structure. A first gate structure is formed across the first fin structure and a second gate structure is formed across the second fin structure. A gate isolation structure is formed between the first fin structure and the second fin structure and separates the first gate structure from the second gate structure. The gate isolation structure includes a bowl-shaped insulating layer that has a first convex sidewall surface adjacent to the first gate structure and a second convex sidewall surface adjacent to the second gate structure.
    Type: Grant
    Filed: July 8, 2021
    Date of Patent: December 10, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wan-Chen Hsieh, Chung-Ting Ko, Tai-Chun Huang
  • Publication number: 20240395907
    Abstract: A method includes forming a semiconductor layer over a substrate; etching a portion of the semiconductor layer to form a first recess and a second recess; forming a first masking layer over the semiconductor layer; performing a first thermal treatment on the first masking layer, the first thermal treatment densifying the first masking layer; etching the first masking layer to expose the first recess; forming a first semiconductor material in the first recess; and removing the first masking layer.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 28, 2024
    Inventors: Wen-Ju Chen, Chung-Ting Ko, Ya-Lan Chang, Ting-Gang Chen, Tai-Chun Huang, Chi On Chui
  • Publication number: 20240387285
    Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming a semiconductor fin over a substrate; forming an isolation feature adjacent the semiconductor fin; forming a metal-containing compound mask over the isolation feature; annealing the metal-containing compound mask; forming a gate structure over a first portion of the semiconductor fin and a first portion of the metal-containing compound mask, wherein a second portion of the semiconductor fin and a second portion of the metal-containing compound mask are exposed by the gate structure; after forming the gate structure, etching back the second portion of the semiconductor fin; and forming a source/drain structure over the second portion of the semiconductor fin.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 21, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Ting KO, Sung-En LIN, Chi On CHUI
  • Publication number: 20240387729
    Abstract: A method includes etching a first portion and a second portion of a dummy gate stack to form a first opening and a second opening, respectively, and depositing a silicon nitride layer to fill the first opening and the second opening. The deposition of the silicon nitride layer comprises a first process selected from treating the silicon nitride layer using hydrogen radicals, implanting the silicon nitride layer, and combinations thereof. The method further includes etching a third portion of the dummy gate stack to form a trench, etching a semiconductor fin underlying the third portion to extend the trench down into a bulk portion of a semiconductor substrate underlying the dummy gate stack, and depositing a second silicon nitride layer into the trench.
    Type: Application
    Filed: July 17, 2024
    Publication date: November 21, 2024
    Inventors: Chung-Ting Ko, Han-Chi Lin, Chunyao Wang, Ching Yu Huang, Tze-Liang Lee, Yung-Chih Wang
  • Publication number: 20240379348
    Abstract: A method includes placing a semiconductor substrate in a deposition chamber, wherein the semiconductor substrate includes a trench, and performing an atomic layer deposition (ALD) process to deposit a dielectric material within the trench, including flowing a first precursor of the dielectric material into the deposition chamber as a gas phase; flowing a second precursor of the dielectric material into the deposition chamber as a gas phase; and controlling the pressure and temperature within the deposition chamber such that the second precursor condenses on surfaces within the trench as a liquid phase of the second precursor, wherein the liquid phase of the second precursor has capillarity.
    Type: Application
    Filed: July 23, 2024
    Publication date: November 14, 2024
    Inventors: Chung-Ting Ko, Chi On Chui
  • Publication number: 20240371959
    Abstract: A method includes forming a first fin structure and a second fin structure protruding from a substrate, forming a dielectric fin between the first fin structure and the second fin structure, recessing the dielectric fin to form a trench between the first fin structure and the second fin structure, and depositing a first dielectric layer on sidewall surfaces of the trench and on a top surface of the recessed dielectric fin. After the depositing the first dielectric layer, a second dielectric layer is deposited in the trench. The method further includes depositing a third dielectric layer to cap the second dielectric layer in the trench, and forming a gate structure on the first fin structure, the second fin structure, and the third dielectric layer.
    Type: Application
    Filed: July 17, 2024
    Publication date: November 7, 2024
    Inventors: Chih-Chung Chang, Sung-En Lin, Chung-Ting Ko, You-Ting Lin, Yi-Hsiu Liu, Po-Wei Liang, Jiun-Ming Kuo, Yung-Cheng Lu, Chi On Chui, Yuan-Ching Peng, Jen-Hong Chang
  • Publication number: 20240363432
    Abstract: A method includes forming a semiconductor fin protruding higher than top surfaces of isolation regions. The isolation regions extend into a semiconductor substrate. The method further includes etching a portion of the semiconductor fin to form a trench, filling the trench with a first dielectric material, wherein the first dielectric material has a first bandgap, and performing a recessing process to recess the first dielectric material. A recess is formed between opposing portions of the isolation regions. The recess is filled with a second dielectric material. The first dielectric material and the second dielectric material in combination form an additional isolation region. The second dielectric material has a second bandgap smaller than the first bandgap.
    Type: Application
    Filed: July 9, 2024
    Publication date: October 31, 2024
    Inventors: Chung-Ting Ko, Chi On Chui
  • Publication number: 20240363707
    Abstract: A semiconductor device is provided. The semiconductor device includes a source/drain structure, a contact structure, a glue layer, a barrier layer, and a silicide layer. The contact structure is over the source/drain structure. The glue layer surrounds the contact structure. The barrier layer is formed on at least a portion of a sidewall surface of the contact structure. The silicide layer is between the source/drain structure and the contact structure, and the silicide layer is in direct contact with the glue layer. The bottom surface of the glue layer is lower than the top surface of the source/drain structure and the bottom surface of the barrier layer.
    Type: Application
    Filed: July 10, 2024
    Publication date: October 31, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Wen HUANG, Chung-Ting KO, Hong-Hsien KE, Chia-Hui LIN, Tai-Chun HUANG
  • Publication number: 20240363429
    Abstract: A semiconductor device includes a fin disposed on a substrate, a first dielectric layer disposed over the fin, a first contact extending through the first dielectric layer to a first depth and electrically coupled to the fin, and a second contact extending through the first dielectric layer to a second depth different than the first depth. The first contact has a first bottom portion having a first cross-sectional shape profile. The second contact being electrically isolated from the fin and having a second bottom portion having a second cross-sectional shape profile different than the first cross-sectional shape profile. The semiconductor device also includes a first protective layer disposed along the first contact without being disposed on at least a portion of the first bottom portion of the first contact, and a second protective layer disposed along the second contact including along the second bottom portion of the second contact.
    Type: Application
    Filed: July 12, 2024
    Publication date: October 31, 2024
    Inventors: Yun Lee, Chung-Ting Ko, Chen-Ming Lee, Mei-Yun Wang, Fu-Kai Yang