Abstract: Middle-of-line (MOL) interconnects and corresponding techniques for forming the MOL interconnects are disclosed herein. An exemplary MOL interconnect structure includes a barrier-free source/drain contact, a barrier-free source/drain via, and a barrier-free gate via disposed in an insulator layer. The barrier-free source/drain is disposed on an epitaxial source/drain, and the barrier-free source/drain contact includes tungsten, molybdenum, or a combination thereof. The barrier-free source/drain via is disposed on the barrier-free source/drain contact and the barrier-free source/drain via includes molybdenum. The barrier-free gate via is disposed on a gate stack disposed adjacent to the epitaxial source/drain, and the barrier-free gate via includes tungsten, molybdenum, or a combination thereof. A width of the barrier-free source/drain via and/or the barrier-free gate via may be less than about 16 nm. The barrier-free source/drain via and/or the barrier-free gate via may be formed at the same time (e.g.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a first side and a second side opposing the first side, a source/drain epitaxial feature disposed adjacent the first side of the substrate, wherein the source/drain epitaxial feature comprises a first epitaxial layer, a second epitaxial layer in contact with the first epitaxial layer, and a third epitaxial layer having sidewalls surrounded by and in contact with the second epitaxial layer. The device structure also includes a first silicide layer in contact with the substrate, the first, second, and third epitaxial layers, a first source/drain contact extending through the substrate from the first side to the second side, and a first metal capping layer disposed between the first silicide layer and the first source/drain contact.

Abstract: A semiconductor device includes a forksheet structure extending lengthwise along a first direction over a substrate. The forksheet structure has a dielectric wall separating a stack of n-type nanostructures from a stack of p-type nanostructures. A gate structure is over the forksheet structure, the gate structure extending lengthwise along a second direction perpendicular to the first direction. The gate structure is in direct contact with the stack of n-type and p-type nanostructures and in direct contact with the dielectric wall. A first gate interconnect is over and in direct contact with the gate structure and a first gate via is over and in direct contact with the first gate interconnect.

Abstract: A method includes forming a first gate spacer and a second gate spacer on a sidewall of a first gate structure. The first gate spacer is between the second gate spacer and the first gate structure. A first interlayer dielectric (ILD) layer is formed to surround the first gate spacer, the second gate spacer, and the first gate structure. A portion of the second gate spacer and a portion of the first ILD layer are removed simultaneously. A top surface of the second gate spacer is lower than a top surface of the first ILD layer.

Abstract: A semiconductor device includes a substrate, a stack of semiconductor nanosheets, a dielectric wall, and a gate structure. The substrate includes a nanosheet mesa, and the stack of semiconductor nanosheets is disposed on the nanosheet mesa. The dielectric wall crosses through the nanosheet mesa and the stack of semiconductor nanosheets. The gate structure wraps the stack of semiconductor nanosheets and crosses over the dielectric wall, wherein a top of the dielectric wall has a recess.

Abstract: Semiconductor structures and methods of forming the same are provided. A semiconductor structure according to the present disclosure includes an active region having a channel region and a source/drain region, a gate structure over the channel region, a gate spacer layer disposed over the channel region and extending along a sidewall of the gate structure, an epitaxial source/drain feature over the source/drain region, a contact etch stop layer (CESL) disposed on the epitaxial source/drain feature and extending along a sidewall of the gate spacer layer, a source/drain contact disposed over the epitaxial source/drain feature, and a dielectric cap layer disposed over the gate structure, the gate spacer layer and at least a portion of the CESL. A sidewall of the source/drain contact is in direct contact with a sidewall of the CESL.

Abstract: A method of forming a semiconductor device includes forming a gate structure on a semiconductor substrate. A gate spacer is formed adjacent to the gate structure. The gate spacer includes a first dielectric layer and a second dielectric layer on the first dielectric layer. A plasma treatment is performed to the second dielectric layer. After performing the plasma treatment, at least a portion of the second dielectric layer is removed such that a sidewall of the first dielectric layer is exposed. A dielectric cap is formed on the gate spacer.

Abstract: A method includes forming a gate structure on a substrate; forming a gate spacer on a sidewall of the gate structure; forming a carbon-containing layer on the gate spacer; diffusing carbon from the carbon-containing layer into a portion of the substrate below the gate spacer; forming a recess in the substrate on one side of the gate spacer opposite to the gate structure; and forming an epitaxy feature in the recess of the substrate.

Abstract: A method includes forming a fin extending above an isolation region. A sacrificial gate stack having a first sidewall and a second sidewall opposite the first sidewall is formed over the fin. A first spacer is formed on the first sidewall of the sacrificial gate stack. A second spacer is formed on the second sidewall of the sacrificial gate stack. A patterned mask having an opening therein is formed over the sacrificial gate stack, the first spacer and the second spacer. The patterned mask extends along a top surface and a sidewall of the first spacer. The second spacer is exposed through the opening in the patterned mask. The fin is patterned using the patterned mask, the sacrificial gate stack, the first spacer and the second spacer as a combined mask to form a recess in the fin. A source/drain region is epitaxially grown in the recess.

Abstract: A method includes forming a gate structure on a substrate; forming a gate spacer on a sidewall of the gate structure; forming a carbon-containing layer on the gate spacer; diffusing carbon from the carbon-containing layer into a portion of the substrate below the gate spacer; forming a recess in the substrate on one side of the gate spacer opposite to the gate structure; and forming an epitaxy feature in the recess of the substrate.

Abstract: A method includes forming a fin extending above an isolation region. A sacrificial gate stack having a first sidewall and a second sidewall opposite the first sidewall is formed over the fin. A first spacer is formed on the first sidewall of the sacrificial gate stack. A second spacer is formed on the second sidewall of the sacrificial gate stack. A patterned mask having an opening therein is formed over the sacrificial gate stack, the first spacer and the second spacer. The patterned mask extends along a top surface and a sidewall of the first spacer. The second spacer is exposed through the opening in the patterned mask. The fin is patterned using the patterned mask, the sacrificial gate stack, the first spacer and the second spacer as a combined mask to form a recess in the fin. A source/drain region is epitaxially grown in the recess.

Abstract: A method includes forming a gate structure on a substrate; forming a gate spacer on a sidewall of the gate structure; forming a carbon-containing layer on the gate spacer; diffusing carbon from the carbon-containing layer into a portion of the substrate below the gate spacer; forming a recess in the substrate on one side of the gate spacer opposite to the gate structure; and forming an epitaxy feature in the recess of the substrate.

Abstract: A semiconductor device includes a substrate, a carbon-containing diffusion barrier, a phosphorus-containing source/drain feature, a gate structure, and a gate spacer. The substrate has a channel region. The carbon-containing diffusion barrier is present in the substrate. The phosphorus-containing source/drain feature is present in the substrate, and the carbon-containing diffusion barrier is between the channel region and the phosphorus-containing source/drain feature. The gate is present over the channel region of the substrate. The gate spacer abuts the gate structure and is present over a portion of the phosphorus-containing source/drain feature.

Abstract: A method includes forming a fin extending above an isolation region. A sacrificial gate stack having a first sidewall and a second sidewall opposite the first sidewall is formed over the fin. A first spacer is formed on the first sidewall of the sacrificial gate stack. A second spacer is formed on the second sidewall of the sacrificial gate stack. A patterned mask having an opening therein is formed over the sacrificial gate stack, the first spacer and the second spacer. The patterned mask extends along a top surface and a sidewall of the first spacer. The second spacer is exposed through the opening in the patterned mask. The fin is patterned using the patterned mask, the sacrificial gate stack, the first spacer and the second spacer as a combined mask to form a recess in the fin. A source/drain region is epitaxially grown in the recess.

Abstract: A method includes forming a fin extending above an isolation region. A sacrificial gate stack having a first sidewall and a second sidewall opposite the first sidewall is formed over the fin. A first spacer is formed on the first sidewall of the sacrificial gate stack. A second spacer is formed on the second sidewall of the sacrificial gate stack. A patterned mask having an opening therein is formed over the sacrificial gate stack, the first spacer and the second spacer. The patterned mask extends along a top surface and a sidewall of the first spacer. The second spacer is exposed through the opening in the patterned mask. The fin is patterned using the patterned mask, the sacrificial gate stack, the first spacer and the second spacer as a combined mask to form a recess in the fin. A source/drain region is epitaxially grown in the recess.

Abstract: A method of forming a semiconductor device includes forming a gate structure on a semiconductor substrate. A gate spacer is formed adjacent to the gate structure. The gate spacer includes a first dielectric layer and a second dielectric layer on the first dielectric layer. A plasma treatment is performed to the second dielectric layer. After performing the plasma treatment, at least a portion of the second dielectric layer is removed such that a sidewall of the first dielectric layer is exposed. A dielectric cap is formed on the gate spacer.

Abstract: A method includes forming a fin extending above an isolation region. A sacrificial gate stack having a first sidewall and a second sidewall opposite the first sidewall is formed over the fin. A first spacer is formed on the first sidewall of the sacrificial gate stack. A second spacer is formed on the second sidewall of the sacrificial gate stack. A patterned mask having an opening therein is formed over the sacrificial gate stack, the first spacer and the second spacer. The patterned mask extends along a top surface and a sidewall of the first spacer. The second spacer is exposed through the opening in the patterned mask. The fin is patterned using the patterned mask, the sacrificial gate stack, the first spacer and the second spacer as a combined mask to form a recess in the fin. A source/drain region is epitaxially grown in the recess.

Abstract: A semiconductor device includes a semiconductor substrate, at least one gate stack, a gate spacer and a dielectric cap. The gate stack is located on the semiconductor substrate. The gate spacer is located on a sidewall of the gate stack. The gate spacer includes a first dielectric layer and a second dielectric layer with different etch properties. The dielectric cap at least caps the gate spacer. The dielectric cap and the second dielectric layer define a gap therebetween.

Abstract: In a method of manufacturing a semiconductor device, a first fin structure for an n-channel fin field effect transistor (FinFET) is formed over a substrate. An isolation insulating layer is formed over the substrate such that an upper portion of the first fin structure protrudes from the isolation insulating layer. A gate structure is formed over a part of the upper portion of the first fin structure. A first source/drain (S/D) epitaxial layer is formed over the first fin structure not covered by the gate structure. A cap epitaxial layer is formed over the first S/D epitaxial layer. The first S/D epitaxial layer includes SiP, and the cap epitaxial layer includes SiC with a carbon concentration is in a range from 0.5 atomic % to 5 atomic %.

Abstract: A method includes forming a fin extending above an isolation region. A sacrificial gate stack having a first sidewall and a second sidewall opposite the first sidewall is formed over the fin. A first spacer is formed on the first sidewall of the sacrificial gate stack. A second spacer is formed on the second sidewall of the sacrificial gate stack. A patterned mask having an opening therein is formed over the sacrificial gate stack, the first spacer and the second spacer. The patterned mask extends along a top surface and a sidewall of the first spacer. The second spacer is exposed through the opening in the patterned mask. The fin is patterned using the patterned mask, the sacrificial gate stack, the first spacer and the second spacer as a combined mask to form a recess in the fin. A source/drain region is epitaxially grown in the recess.