Abstract: A chip package structure includes a multi-layer circuit layer and at least one chip. The multi-layer circuit layer has a first surface and a second surface opposite to each other, and includes a high-density circuit layer, a medium-density circuit layer and a low-density circuit layer. The high-density circuit layer has a first surface. The medium-density circuit layer is located between the high-density circuit layer and the low-density circuit layer. The low-density circuit layer has a second surface. The high-density circuit layer has a first line width, the medium-density circuit layer has a second line width, and the low-density circuit layer has a third line width. The first line width is less than the second line width, and the second line width is less than the third line width. The chip is disposed on the first surface of the high-density circuit layer and is electrically connected to the multi-layer circuit layer.

Abstract: A package structure includes a multi-layer circuit layer, multiple components, and a stress adjustment board. The multi-layer circuit layer has a first surface and a second surface opposite to each other. The components are configured on the first surface of the multi-layer circuit layer and electrically connected to the multi-layer circuit layer. The stress adjustment board is configured on the second surface of the multi-layer circuit layer. The stress adjustment board includes a copper layer and has multiple conductive vias. The conductive vias are electrically connected to the multi-layer circuit layer. A first peripheral surface of the multi-layer circuit layer is aligned with a second peripheral surface of the stress adjustment board.

Abstract: A package carrier includes a redistribution circuit layer, a plurality of first conductive pillars, and a package mold plate. The redistribution circuit layer has a first surface and a second surface opposite to each other, and includes a plurality of redistribution circuits, a plurality of conductive vias, a plurality of dielectric layers, and a plurality of output pads. The conductive vias are flush with the first surface, and the output pads protrude from the second surface. The first conductive pillars are disposed within the package mold plate, and are adjacent to the first surface of the redistribution circuit layer and also electrically connected to part of the conductive vias. The package mold plate is adjacent to the first surface of the redistribution circuit layer and has a recess in a middle region of the package mold plate. The recess exposes the first conductive pillars.

Abstract: A package carrier includes a signal board, a power board and a connection layer. The signal board includes a plurality of first circuits. The power board includes a plurality of second circuits. A line width of each of the first circuits is less than a line width of each of the second circuits, and a first thickness of the signal board is less than a second thickness of the power board. The connection layer is disposed between the signal board and the power board, wherein the power board is electrically connected to the signal board through the connection layer.

Abstract: A chip carrier and a manufacturing method thereof are provided. The chip carrier includes a first structure layer and a second structure layer. The first structure layer has at least one opening and includes at least one first insulating layer. A thermal expansion coefficient of the first insulating layer is between 2 ppm/° C. and 5 ppm/° C. The second structure layer is disposed on the first structure layer and defines at least one cavity with the first structure layer. The second structure layer includes at least one second insulating layer, and a thermal expansion coefficient of the second insulating layer is equal to or greater than the thermal expansion coefficient of the first insulating layer.

Abstract: A manufacturing method of a chip package structure is provided. A carrier board with an accommodating cavity, a substrate, and a stainless steel layer sputtered on the substrate is disposed. A chip is disposed in the accommodating cavity of the carrier board. The chip has an active surface, a back surface opposite to the active surface, and multiple electrodes disposed on the active surface. A circuit structure layer is formed on the carrier board. The circuit structure layer includes a patterned circuit and multiple conductive vias. The patterned circuit is electrically connected to the electrodes of the chip through the conductive vias. An encapsulant is formed to cover the active surface of the chip and the circuit structure layer. The active surface of the chip and a bottom surface of the encapsulant are coplanar. The carrier board is removed to expose the chip disposed in the accommodating cavity.

Abstract: A manufacturing method a chip package structure. The carrier board includes a substrate and a stainless steel layer sputtered on the substrate. The substrate has multiple first cavities and at least one second cavity. The stainless steel layer conformally covers the first cavities and the second cavity to define multiple third cavities and at least one fourth cavity. Conductive blocks fill the third cavities. At least one metal layer covers the stainless steel layer, the conductive blocks, and the fourth cavity to define at least one fifth cavity. At least one chip is disposed inside the fifth cavity. At least one circuit structure layer is formed on the carrier board. A patterned circuit layer of the circuit structure layer is electrically connected with multiple electrodes of the chip. The carrier board and the circuit structure layer are separated to expose the conductive blocks and the metal layer.

Abstract: A manufacturing method of a circuit board is provided. A first carrier board included a substrate and a first conductive layer is provided, and the first conductive layer is located on a first surface of the substrate. A stainless steel layer is sputtered on the first conductive layer. An insulating layer is formed to cover a peripheral region of the stainless steel layer and expose a central region. A circuit structure layer is formed on the central region exposed by the insulating layer. A bottom surface of the circuit structure layer is connected to the first carrier board. A transferring procedure is performed to adhere a top surface of the circuit structure layer onto an adhesive layer of a second carrier board. The first carrier board is separated with the circuit structure layer to transfer the circuit structure layer onto the second carrier board, and expose the bottom surface of the circuit structure layer.

Abstract: A circuit board including an electronic device and a manufacturing method of the circuit board are provided. The manufacturing method includes: providing a stainless steel base material including a first surface and a second surface opposite to each other, at least one first cavity located at the first surface and at least one second cavity located at the second surface; respectively forming a first and a second metal layers on the stainless steel base material; respectively disposing at least one first and at least one second electronic devices in the first and the second cavities; respectively forming a first and a second insulating layers on the first and the second surfaces; respectively forming a first and a second circuit structures on the first and the second insulating layers, separating the stainless steel base material, the first and the second metal layers to form two separate circuit substrates including electronic devices.

Abstract: A method of fabricating a packaging substrate includes following steps: providing a carrier board having two opposite surfaces, forming on each of the surfaces a plurality of first metal bumps; covering the carrier board and the first metal bumps with a first dielectric layer that has a plurality of first intaglios which exposes a top surface and side surface of the first metal bumps; forming a conductive seedlayer on the first dielectric layer and the first metal bumps; forming a metal layer on the conductive seedlayer; removing a portion of the metal layer and the conductive seedlayer that is higher than the top surface of the first dielectric layer, and forming a first circuit layer in the first intaglios; forming a built-up structure on the first circuit layer and the first dielectric layer, forming a pair of upper and lower entire packaging substrates.

Abstract: A fabrication method of a coreless packaging substrate is provided, including the steps of: forming an inner built-up circuit board on a carrier; removing the carrier; and symmetrically forming a first outer built-up structure and a second outer built-up structure on top and bottom surfaces of the inner built-up circuit board, respectively. The present invention effectively increases the product yield, saves the fabrication cost, and reduces wastes.

Abstract: A coreless packaging substrate includes: a circuit buildup structure having at least a dielectric layer, a wiring layer and a plurality of conductive elements, a plurality of electrical pads embedded in the dielectric layer of the circuit buildup structure, a plurality of metal bumps formed on the wiring layer of the circuit buildup structure, and a dielectric passivation layer formed on the surface of the circuit buildup structure and the metal bumps with the metal bumps exposed from the dielectric passivation layer. The metal bumps each have a metal column portion and a wing portion integrally connected to the metal column portion, such that the bonding force between the metal bumps and a semiconductor chip can be enhanced by the entire top surface of the wing portions of the metal bumps being completely exposed.

Abstract: A coreless packaging substrate includes: a circuit buildup structure having at least a dielectric layer, a wiring layer and a plurality of conductive elements, a plurality of electrical pads embedded in the dielectric layer of the circuit buildup structure, a plurality of metal bumps formed on the wiring layer of the circuit buildup structure, and a dielectric passivation layer formed on the surface of the circuit buildup structure and the metal bumps with the metal bumps exposed from the dielectric passivation layer. The metal bumps each have a metal column portion and a wing portion integrally connected to the metal column portion, such that the bonding force between the metal bumps and a semiconductor chip can be enhanced by the entire top surface of the wing portions of the metal bumps being completely exposed.

Abstract: A coreless packaging substrate is provided which includes: a circuit buildup structure having at least a dielectric layer, at least a wiring layer and a plurality of conductive elements, a plurality of electrical pads embedded in the lowermost one of the at least a dielectric layer, a plurality of metal bumps formed on the uppermost one of the at least a wiring layer, and a dielectric passivation layer formed on the surface of the uppermost one of the circuit buildup structure and the metal bumps, with the metal bumps exposed from the dielectric passivation layer. The metal bumps each have a metal column portion and a wing portion integrally connected to the metal column portion, such that the bonding force between the metal bumps and a semiconductor chip is enhanced by the entire top surface of the wing portions of the metal bumps being completely exposed.

Abstract: A process of electronic structure is provided. First, a carrier board is provided, in which the carrier board has a first surface. Next, a first release layer is formed on the first surface of the carrier board. The first release layer has property of withstanding high-temperature and temporary adhesion capability and the first release layer entirely or mostly overlays the first surface. Then, a built-up structure is formed on the first release layer. Finally, a separating process is performed so that the built-up structure is separated from the carrier board to form an electronic structure.

Abstract: A packaging substrate includes a first dielectric layer; a plurality of first conductive pads embedded in and exposed from a first surface of the first dielectric layer; a first circuit layer embedded in and exposed from a second surface of the first dielectric layer; a plurality of first metal bumps disposed in the first dielectric layer, each of the first metal bumps having a first end embedded in the first circuit layer and a second end opposing the first end and disposed on one of the first conductive pads, a conductive seedlayer being disposed between the first circuit layer and the first dielectric layer and between the first circuit layer and the first metal bump; a built-up structure disposed on the first circuit layer and the first dielectric layer; and a plurality of second conductive pads disposed on the built-up structure. The packaging substrate has an over-warpage problem improved.

Abstract: A packaging substrate includes a first dielectric layer, a first circuit layer, a first metal bump, and a built-up structure. The first metal bump and the first circuit layer are embedded in and exposed from two surfaces of the first dielectric layer. The end of the first metal bump is embedded in the first circuit layer and between the first circuit layer and the first dielectric layer. In addition, a conductive seedlayer is disposed between the first circuit layer and the first metal bump. The built-up structure is disposed on the first circuit layer and the first dielectric layer. The outmost layer of the built-up structure has a plurality of conductive pads. Compared to the prior art, the present invention can effectively improve the warpage problem of the conventional packaging substrate.

Abstract: An edge separation equipment and an operating method thereof are suitable for a carrier and a circuit board in a coreless process. The carrier is attached to the circuit board by a mechanically separable interface, and the edge separation equipment is used to separate the edge of the carrier from the edge of the circuit board. The edge separation equipment includes a platform, a supporting device and a wind knife device. The platform has a supporting surface on which the carrier or the circuit board is mounted. The supporting device is configured at a side of the platform. The wind knife device is configured on the supporting device, and the air jet supplied by the wind knife device blows toward the edge of the carrier and the edge of the circuit board, such that there is an edge separation width between the carrier and the circuit board.

Abstract: A packaging substrate includes a first dielectric layer, a first circuit layer, a first metal bump, and a built-up structure. The first metal bump and the first circuit layer are embedded in and exposed from two surfaces of the first dielectric layer. The end of the first metal bump is embedded in the first circuit layer and between the first circuit layer and the first dielectric layer. In addition, a conductive seedlayer is disposed between the first circuit layer and the first metal bump. The built-up structure is disposed on the first circuit layer and the first dielectric layer. The outmost layer of the built-up structure has a plurality of conductive pads. Compared to the prior art, the present invention can effectively improve the warpage problem of the conventional packaging substrate.

Abstract: A coreless package substrate is provided, including: a circuit buildup structure including at least a dielectric layer, at least a circuit layer and conductive elements; first electrical contact pads embedded in the lowermost dielectric layer of the circuit buildup structure; a plurality of metal bumps formed on the uppermost circuit layer of the circuit buildup structure; a dielectric passivation layer disposed on a top surface of the circuit buildup structure and the metal bumps; and second electrical contact pads embedded in the dielectric passivation layer and electrically connected to the metal bumps. With the second electrical contact pads being engaged with the metal bumps and having top surfaces thereof completely exposed, the bonding strength between the second electrical contact pads and a chip to be mounted thereon and between the second electrical contact pads and the metal bumps can be enhanced.