Abstract: A single-poly flash memory cell has a control device, a switch device, and an erase device, all of which share a common polysilicon floating gate which is designed to retain charge in the programmed memory cell. The memory cell is erased by applying an erase voltage to the tub of the erase device to cause tunneling across the oxide layer separating the floating gate from the rest of the erase device structure. Since a typical tub-to-source/drain breakdown voltage (e.g., 15 volts) is greater than a typical erase voltage (e.g., 10 volts), the memory cell can be safely erased without risking the junction breakdowns that are associated with other prior art single-poly memory cell designs for deep sub-micron technologies (e.g., 0.25-micron and lower).

Abstract: A method for wet etching disposable spacers in silicon integrated circuits is provided. Illustratively, a pair of spacers is formed over a polysilicon substrate. A second pair of spacers is formed from doped silicon dioxide over the first pair of spacers. Then the second pair of spacers is etched away with NH.sub.4 OH/H.sub.2 O.sub.2, thus providing a means for defining the underlying polysilicon layer, e.g., by etching.

Abstract: Defect density in a semiconductor process sequence that uses two local oxidations is reduced by using an approximately 1:1 ratio of nitride to oxide thickness in the second local oxidation step and an annealing step.

Abstract: In the manufacture of semiconductor integrated-circuit devices, electrical contact to semiconductor regions such as, e.g., source and drain regions of field-effect transistors typically is made by a structure in which a silicide is intermediary to silicon and metal. The invention provides for processing, after window formation and before metal deposition, which includes deposition of a silicide-forming material, and annealing in a non-oxidizing atmosphere. Preferably, the atmosphere includes a component which forms a conductive compound with the silicide-forming material. Resulting contact structures have good step coverage, low contact resistance, low interdiffusion of metal into semiconductor, and fail-safe operation in the event of breaks due to electromigration. Moreover, in the case of misalignment of a window, a contact region may be extended laterally by dopant diffusion, thereby safeguarding the junction. Tolerance to window misalignment permits increased packing density, e.g.

Abstract: A p-type tub in a CMOS integrated circuit is isolated from the adjacent n-type tub by means of a field oxide having a p-type channel stop region formed by a boron ion implant. The depth of the ion implant is selected so that the peak of the boron concentration is located immediately under the field oxide region that is subsequently grown. In addition, the implant is allowed to penetrate into the active device regions, producing a retrograde boron concentration in the n-channel region. This technique simultaneously improves device isolation and n-channel transistor punch-through characteristics, allowing the extension of CMOS technology to sub-micron device geometries.

Abstract: When making CMOS logic circuits, for example an inverter, it is frequently necessary to connect the sources of the p and n channel transistors to their respective tubs (n and p, respectively). The prior art required either a large contact window covering both source and tub regions, or else two standard size contact windows. The present technique forms the tub tie connection by the use of the same silicide layer that is formed on the source/drain regions, which typically also forms a gate silicide in the self-aligned silicide (i.e., "salicide") process. A conventional window may then be used to connect the silicide tub tie (and hence the source/tub regions) to a power supply conductor. A space saving is obtained, and increased freedom for placing the power supply contact window is obtained.

Abstract: Silicides are important for submicron VLSIC technology. Problems have been found in forming silicides by known techniques involving simply depositing a metal film and heating that metal to form a silicide layer. This invention solves the problems through recognition that polymeric contamination can be left on the surface from commonly-used previous reactive ion etch steps, and removes any such contamination to metal deposition by the additional step of heating in dry oxygen at a low temperature, such as 800 degrees Centigrade, before the contamination has been significantly hardened.

Abstract: A method of reducing the time and temperature for either flowing or re-flowing a glass layer on a semiconductor device is described. The method involves conducting the flow or re-flow process steps at an elevated pressure which reduces both the time and the temperature required to achieve proper flow and re-flow characteristics.