Patents by Inventor Chung-Wei Wang
Chung-Wei Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11964881Abstract: A method for making iridium oxide nanoparticles includes dissolving an iridium salt to obtain a salt-containing solution, mixing a complexing agent with the salt-containing solution to obtain a blend solution, and adding an oxidating agent to the blend solution to obtain a product mixture. A molar ratio of a complexing compound of the complexing agent to the iridium salt is controlled in a predetermined range so as to permit the product mixture to include iridium oxide nanoparticles.Type: GrantFiled: July 27, 2020Date of Patent: April 23, 2024Assignee: NATIONAL YANG MING CHIAO TUNG UNIVERSITYInventors: Pu-Wei Wu, Yi-Chieh Hsieh, Han-Yi Wang, Kuang-Chih Tso, Tzu-Ying Chan, Chung-Kai Chang, Chi-Shih Chen, Yu-Ting Cheng
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Patent number: 11961840Abstract: A semiconductor device structure is provided. The device includes one or more first semiconductor layers, each first semiconductor layer of the one or more first semiconductor layers is surrounded by a first intermixed layer, wherein the first intermixed layer comprises a first material and a second material.Type: GrantFiled: August 9, 2022Date of Patent: April 16, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Mao-Lin Huang, Lung-Kun Chu, Chung-Wei Hsu, Jia-Ni Yu, Kuo-Cheng Chiang, Kuan-Lun Cheng, Chih-Hao Wang
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Publication number: 20240120402Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a first dielectric feature extending along a first direction, the first dielectric feature comprising a first dielectric layer having a first sidewall and a second sidewall opposing the first sidewall, a first semiconductor layer disposed adjacent the first sidewall, the first semiconductor layer extending along a second direction perpendicular to the first direction, a second dielectric feature extending along the first direction, the second dielectric feature disposed adjacent the first semiconductor layer, and a first gate electrode layer surrounding at least three surfaces of the first semiconductor layer, and a portion of the first gate electrode layer is exposed to a first air gap.Type: ApplicationFiled: November 19, 2023Publication date: April 11, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jia-Ni YU, Kuo-Cheng CHIANG, Mao-Lin HUANG, Lung-Kun CHU, Chung-Wei HSU, Chun-Fu LU, Chih-Hao WANG, Kuan-Lun CHENG
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Publication number: 20240113195Abstract: Semiconductor structures and methods for forming the same are provided. The semiconductor structure includes a plurality of first nanostructures formed over a substrate, and a dielectric wall adjacent to the first nanostructures. The semiconductor structure also includes a first liner layer between the first nanostructures and the dielectric wall, and the first liner layer is in direct contact with the dielectric wall. The semiconductor structure also includes a gate structure surrounding the first nanostructures, and the first liner layer is in direct contact with a portion of the gate structure.Type: ApplicationFiled: February 22, 2023Publication date: April 4, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jia-Ni YU, Lung-Kun CHU, Chun-Fu LU, Chung-Wei HSU, Mao-Lin HUANG, Kuo-Cheng CHIANG, Chih-Hao WANG
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Patent number: 11949001Abstract: The present disclosure provides a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes channel members disposed over a substrate, a gate structure engaging the channel members, and an epitaxial feature adjacent the channel members. At least one of the channel members has an end portion in physical contact with an outer portion of the epitaxial feature. The end portion of the at least one of the channel members includes a first dopant of a first concentration. The outer portion of the epitaxial feature includes a second dopant of a second concentration. The first concentration is higher than the second concentration.Type: GrantFiled: March 21, 2022Date of Patent: April 2, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Ching Wang, Chung-I Yang, Jon-Hsu Ho, Wen-Hsing Hsieh, Kuan-Lun Cheng, Chung-Wei Wu, Zhiqiang Wu
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Patent number: 11948987Abstract: A semiconductor device according to the present disclosure includes a source feature and a drain feature, a plurality of semiconductor nanostructures extending between the source feature and the drain feature, a gate structure wrapping around each of the plurality of semiconductor nanostructures, a bottom dielectric layer over the gate structure and the drain feature, a backside power rail disposed over the bottom dielectric layer, and a backside source contact disposed between the source feature and the backside power rail. The backside source contact extends through the bottom dielectric layer.Type: GrantFiled: September 9, 2020Date of Patent: April 2, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Lung-Kun Chu, Mao-Lin Huang, Chung-Wei Hsu, Jia-Ni Yu, Kuo-Cheng Chiang, Kuan-Lun Cheng, Chih-Hao Wang
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Publication number: 20240100880Abstract: A multi-piece wheel frame includes a rim and a disc. The rim includes a barrel, and an outer rim portion protruding outwardly from the barrel. The outer rim portion forms an inclined surface, and a ring edge surface connected to an outer edge of the inclined surface and cooperating with the inclined surface to form an obtuse angle. The disc is fixed to the rim, and includes a disc core, a plurality of spoke portions extending radially outwardly from the disc core, and a reinforced ring portion connected to the spoke portions and fixed to the outer rim portion. The reinforced ring portion abuts against at least one of the inclined surface and the ring edge surface.Type: ApplicationFiled: November 16, 2022Publication date: March 28, 2024Inventors: Te-Fu HSIAO, Che-Hao KUO, Chung-Hsin CHANG, Chia-Hsin WANG, Erh-Wei LIU
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Publication number: 20240107414Abstract: This disclosure provides systems, methods and apparatus, including computer programs encoded on computer storage media, for switching a secondary cell to a primary cell. A user equipment (UE) monitors a first radio condition of the UE for beams of a primary cell and a second radio condition for beams of one or more secondary cells configured for the UE in carrier aggregation. The UE transmits a request to configure a candidate beam of at least one candidate secondary cell as a new primary cell in response to the first radio condition not satisfying a first threshold and the second radio condition for the at least one candidate secondary cell satisfying a second threshold. A base station determines to reconfigure at least one secondary cell as the new primary cell. The base station and the UE perform a handover of the UE to the new primary cell.Type: ApplicationFiled: September 23, 2022Publication date: March 28, 2024Inventors: Yu-Chieh HUANG, Kuhn-Chang LIN, Jen-Chun CHANG, Wen-Hsin HSIA, Chia-Jou LU, Sheng-Chih WANG, Chenghsin LIN, Yeong Leong CHOO, Chun-Hsiang CHIU, Chihhung HSIEH, Kai-Chun CHENG, Chung Wei LIN
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Publication number: 20240096880Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a first channel structure configured to transport charge carriers within a first transistor device and a first gate electrode layer wrapping around the first channel structure. A second channel structure is configured to transport charge carriers within a second transistor device. A second gate electrode layer wraps around the second channel structure. The second gate electrode layer continuously extends from around the second channel structure to cover the first gate electrode layer. A third channel structure is configured to transport charge carriers within a third transistor device. A third gate electrode layer wraps around the third channel structure. The third gate electrode layer continuously extends from around the third channel structure to cover the second gate electrode layer.Type: ApplicationFiled: November 16, 2023Publication date: March 21, 2024Inventors: Mao-Lin Huang, Chih-Hao Wang, Kuo-Cheng Chiang, Jia-Ni Yu, Lung-Kun Chu, Chung-Wei Hsu
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Patent number: 11933999Abstract: An optical structure film and a light source module are provided. The optical structure film includes multiple optical unit microstructures. Each of the optical unit microstructures has four side surfaces and an inwardly concave beam splitting surface. The beam splitting surface is respectively connected to the side surfaces, and the beam splitting surface has four endpoints when viewed from a front viewing angle. Connection lines of the four endpoints form a rectangle. The beam splitting surface includes at least one beam splitting curved surface. A junction of the at least one beam splitting curved surface and one of the four side surfaces is a first line segment. A projection of a midpoint of an edge of the rectangle on the beam splitting surface overlaps with a relative extreme point of the first line segment.Type: GrantFiled: December 1, 2022Date of Patent: March 19, 2024Assignee: Coretronic CorporationInventors: Wen-Chun Wang, Chih-Jen Tsang, Chung-Wei Huang
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Publication number: 20240019915Abstract: A computer-implemented method of managing a thermal policy of an information handling system involves identifying a first power associated with a central processing unit (CPU) of the information handling system, identifying a first time duration of a first workload associated with the CPU, accessing a table indicating, for combinations of workload time durations and CPU power, a ramp rate and a thermal management mode, comparing the first power and the first time duration with the table to identify a first ramp rate and a first thermal management mode associated with the first power and the first time duration, and placing the CPU and a fan of the information handling system in the first thermal management mode and adjusting a fan speed of the fan based on the first ramp rate.Type: ApplicationFiled: July 18, 2022Publication date: January 18, 2024Inventors: TseAnGino Chu, Ting-Chiang Huang, Chung-Wei Wang, Qinghong He
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Patent number: 11592890Abstract: Embodiments of a system, method, and memory storage device for managing performance optimization of applications executed by an Information Handling System (IHS) are described. In an illustrative, non-limiting embodiment, an IHS may include computer-executable instructions to receive telemetry data associated with an operating behavior of the IHS. Using the telemetry data, the IHS generates a profile recommendation from the received telemetry data using a machine learning (ML) service, and adjusts a core stall management mechanism of a second processor to optimize a performance of the IHS. The second processor performs at least a portion of the operating behavior of the IHS.Type: GrantFiled: March 1, 2021Date of Patent: February 28, 2023Assignee: Dell Products, L.P.Inventors: Chia-Chi Ho, Thomas Alexander Shows, Ya-Chen Tsai, Chung-Wei Wang, Yi-Chung Cheng
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Patent number: 11513810Abstract: A method of configuring a display device interface (DDI) detects a trigger signal, generated by a display device. If the trigger signal is associated with a power on event, a full configuration of the DDI is performed, including loading display device capability information provided by the display device into DDI configuration registers and setting one or more DDI configuration parameters accordingly. If the trigger signal is associated with resume event, rather than a power on event, a modified fast link resume operation may be performed to route the trigger signal to a controller configured to explicitly write display device capability information to the appropriate DDI configuration registers before setting the corresponding DDI configuration parameter accordingly. The DDI may include a re-timer, between the DDI source and sink, configured to snoop the explicit write transaction such that the re-timer configuration is also updated.Type: GrantFiled: July 15, 2021Date of Patent: November 29, 2022Assignee: Dell Products L.P.Inventors: Chung-Wei Wang, Chih-Chung Lin, You-Liang Chen, Pei-Yu Wang
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Publication number: 20220276690Abstract: Embodiments of a system, method, and memory storage device for managing performance optimization of applications executed by an Information Handling System (IHS) are described. In an illustrative, non-limiting embodiment, an IHS may include computer-executable instructions to receive telemetry data associated with an operating behavior of the IHS. Using the telemetry data, the IHS generates a profile recommendation from the received telemetry data using a machine learning (ML) service, and adjusts a core stall management mechanism of a second processor to optimize a performance of the IHS. The second processor performs at least a portion of the operating behavior of the IHS.Type: ApplicationFiled: March 1, 2021Publication date: September 1, 2022Applicant: Dell Products, L.P.Inventors: Chia-Chi Ho, Thomas Alexander Shows, Ya-Chen Tsai, Chung-Wei Wang, Yi-Chung Cheng
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Patent number: 11187845Abstract: A backlight module includes a light guide plate, a light source, a prism sheet, and a reflective film. The light source is disposed on a light-incident surface of the light guide plate. The prism sheet is disposed on a light exit surface of the light guide plate, and includes a plurality of first prism structures that protrude toward the light exit surface of the light guide plate. The reflective film is disposed on a reflection surface of the light guide plate, and includes a film body, a plurality of second prism structures that are disposed on the film body and that protrude from the film body toward the reflection surface, and a light absorbing layer that is disposed on the film body opposite to the second prism structures.Type: GrantFiled: July 30, 2020Date of Patent: November 30, 2021Assignee: OPTIVISION TECHNOLOGY INC.Inventors: Chung-Wei Wang, Li-Jen Hsu
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Publication number: 20210325597Abstract: A backlight module includes a light guide plate, a light source, a prism sheet, and a reflective film. The light source is disposed on a light-incident surface of the light guide plate. The prism sheet is disposed on a light exit surface of the light guide plate, and includes a plurality of first prism structures that protrude toward the light exit surface of the light guide plate. The reflective film is disposed on a reflection surface of the light guide plate, and includes a film body, a plurality of second prism structures that are disposed on the film body and that protrude from the film body toward the reflection surface, and a light absorbing layer that is disposed on the film body opposite to the second prism structures.Type: ApplicationFiled: July 30, 2020Publication date: October 21, 2021Inventors: Chung-Wei WANG, Li-Jen HSU
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Patent number: 10816156Abstract: Provided are a light guiding element (100), a light guiding device (500), and a lighting module (800). The light guiding element (100) includes a light incident portion (1) and a light exit portion (2), where the light incident portion (1) includes a plurality of light guiding columns (11), each of which includes a first end surface (A) connected to the light exit portion (2), a second end surface (B) facing away from the light exit portion, and a side surface formed between the first end surface (A) and the second end surface (B), where the first end surface (A) has an area larger than that of the second end surface (B). Also provided are a light guiding device (500) including the light guiding element (100), and a lighting module (800) including the light guiding device (500). The light guiding element (100) enables, for a generated light type pattern, the shape to be complete, the color to be even, and the phenomena of vignette effect and dark lines to be reduced.Type: GrantFiled: February 13, 2018Date of Patent: October 27, 2020Assignee: Everlight Electronics Co., Ltd.Inventors: Yi-Hui Liao, Chung-Wei Wang
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Publication number: 20200003381Abstract: Provided are a light guiding element (100), a light guiding device (500), and a lighting module (800). The light guiding element (100) includes a light incident portion (1) and a light exit portion (2), where the light incident portion (1) includes a plurality of light guiding columns (11), each of which includes a first end surface (A) connected to the light exit portion (2), a second end surface (B) facing away from the light exit portion, and a side surface formed between the first end surface (A) and the second end surface (B), where the first end surface (A) has an area larger than that of the second end surface (B). Also provided are a light guiding device (500) including the light guiding element (100), and a lighting module (800) including the light guiding device (500). The light guiding element (100) enables, for a generated light type pattern, the shape to be complete, the color to be even, and the phenomena of vignette effect and dark lines to be reduced.Type: ApplicationFiled: February 13, 2018Publication date: January 2, 2020Applicant: Everlight Electronics Co., Ltd.Inventors: Yi-Hui LIAO, Chung-Wei WANG
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Patent number: 10355505Abstract: A system, method, and computer-readable medium are disclosed for detecting when a lower power adapter is coupled with an information handling system having higher power requirements. More specifically, in certain embodiments, a circuit (such as an embedded controller (EC)) detects an adapter wattage when an adapter plug-in is detected. If a lower wattage power adapter is detected (e.g., a 45 W power adapter), the embedded controller activates a signal (e.g., an AC_DISABLE signal) to stop powering the information handling system from the adapter. In certain embodiments, the information handling system is powered from a battery associated with the information handling system when the power adapter power capacity does not satisfy the power requirements of the information handling system. In certain embodiments, the circuit substantially simultaneously generates a low power warning. In certain embodiments, the adapter wattage may be detected via an adapter identifier (e.g.Type: GrantFiled: March 10, 2014Date of Patent: July 16, 2019Assignee: Dell Products L.P.Inventors: Adolfo S. Montero, Chung-Wei Wang, Jih-Peng Yeh
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Patent number: 10337689Abstract: The present invention provides a light emitting apparatus and a lighting module, comprising: a circuit substrate, a plurality of optical sources and an optical element; the optical element comprises a translucent element and an interference element; the plurality of light sources are arranged on the circuit substrate for lighting the optical element; the optical element is arranged above the plurality of light sources; and the interference element is arranged on the translucent element, which is used to make light emitted from each of the light sources offset interference in a first polarization direction, enhance interference in a second polarization direction, and emit through the translucent element. The light emitting apparatus and the lighting module of the present invention are employed to provide a more diversified optical pattern to the user and improve the user experience.Type: GrantFiled: February 8, 2018Date of Patent: July 2, 2019Assignee: EVERLIGHT ELECTRONICS CO., LTD.Inventors: Yi-Hui Liao, Chung-Wei Wang, Shun-Chang Li