Abstract: Disclosed is an image display format conversion method, comprising: a frame recognition step of performing a frame recognition process on a comic page image to obtain a plurality of comic frame images and frame position information; a frame sequence determination step of determining a frame viewing sequence according to a selected regional layout rule; and a frame reassembly step of reassembling and converting, based on the frame viewing sequence, the plurality of comic frame images into a digital media in an animation-like format or a scrolling-comic format.

Abstract: Some implementations described herein include systems and techniques for fabricating a stacked die product. The systems and techniques include using a supporting fill mixture that includes a combination of types of composite particulates in a lateral gap region of a stack of semiconductor substrates and along a perimeter region of the stack of semiconductor substrates. One type of composite particulate included in the combination may be a relatively smaller size and include a smooth surface, allowing the composite particulate to ingress deep into the lateral gap region. Properties of the supporting fill mixture including the combination of types of composite particulates may control thermally induced stresses during downstream manufacturing to reduce a likelihood of defects in the supporting fill mixture and/or the stack of semiconductor substrates.

Abstract: A first protective layer is formed on a first die and a second die, and openings are formed within the first protective layer. The first die and the second die are encapsulated such that the encapsulant is thicker than the first die and the second die, and vias are formed within the openings. A redistribution layer can also be formed to extend over the encapsulant, and the first die may be separated from the second die.

Abstract: Provided are FinFET devices and methods of forming the same. A dummy gate having gate spacers on opposing sidewalls thereof is formed over a substrate. A dielectric layer is formed around the dummy gate. An upper portion of the dummy gate is removed and upper portions of the gate spacers are removed, so as to form a first opening in the dielectric layer. A lower portion of the dummy gate is removed to form a second opening below the first opening. A metal layer is formed in the first and second openings. The metal layer is partially removed to form a metal gate.

Abstract: A method for processing an integrated circuit includes forming first and second gate all around transistors. The method forms a dipole oxide in the first gate all around transistor without forming the dipole oxide in the second gate all around transistor. This is accomplished by entirely removing an interfacial dielectric layer and a dipole-inducing layer from semiconductor nanosheets of the second gate all around transistor before redepositing the interfacial dielectric layer on the semiconductor nanosheets of the second gate all around transistor.

Abstract: A semiconductor device structure is provided. The device includes one or more first semiconductor layers, each first semiconductor layer of the one or more first semiconductor layers is surrounded by a first intermixed layer, wherein the first intermixed layer comprises a first material and a second material.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a first dielectric feature extending along a first direction, the first dielectric feature comprising a first dielectric layer having a first sidewall and a second sidewall opposing the first sidewall, a first semiconductor layer disposed adjacent the first sidewall, the first semiconductor layer extending along a second direction perpendicular to the first direction, a second dielectric feature extending along the first direction, the second dielectric feature disposed adjacent the first semiconductor layer, and a first gate electrode layer surrounding at least three surfaces of the first semiconductor layer, and a portion of the first gate electrode layer is exposed to a first air gap.

Abstract: Semiconductor structures and methods for forming the same are provided. The semiconductor structure includes a plurality of first nanostructures formed over a substrate, and a dielectric wall adjacent to the first nanostructures. The semiconductor structure also includes a first liner layer between the first nanostructures and the dielectric wall, and the first liner layer is in direct contact with the dielectric wall. The semiconductor structure also includes a gate structure surrounding the first nanostructures, and the first liner layer is in direct contact with a portion of the gate structure.

Abstract: A semiconductor device according to the present disclosure includes a source feature and a drain feature, a plurality of semiconductor nanostructures extending between the source feature and the drain feature, a gate structure wrapping around each of the plurality of semiconductor nanostructures, a bottom dielectric layer over the gate structure and the drain feature, a backside power rail disposed over the bottom dielectric layer, and a backside source contact disposed between the source feature and the backside power rail. The backside source contact extends through the bottom dielectric layer.

Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a first channel structure configured to transport charge carriers within a first transistor device and a first gate electrode layer wrapping around the first channel structure. A second channel structure is configured to transport charge carriers within a second transistor device. A second gate electrode layer wraps around the second channel structure. The second gate electrode layer continuously extends from around the second channel structure to cover the first gate electrode layer. A third channel structure is configured to transport charge carriers within a third transistor device. A third gate electrode layer wraps around the third channel structure. The third gate electrode layer continuously extends from around the third channel structure to cover the second gate electrode layer.

Abstract: The present invention discloses a double-gate trench-type insulated-gate bipolar transistor device. A first trench and a second trench, which are located in a P-type doped well layer, and separate from each other, are extended into a lightly-doped N-type drift layer. A heavily-doped P-type source region and a heavily-doped N-type source region, which are sequentially connected, are located between the first trench and the second trench, and are arranged at an upper part of the P-type doped well layer in a horizontal direction. The heavily-doped P-type source region is located at a periphery of the second trench, a middle part and the upper part of the P-type doped well layer are provided with an N-type doped well layer and a P-type doped base region layer, respectively. The heavily-doped P-type source region and the heavily-doped N-type source region are both located at an upper part of the P-type doped base region layer.

Abstract: The present invention discloses an apparatus for slew rate enhancement of an operational amplifier, wherein an auxiliary control device and an auxiliary output device are added to the output stage of an operational amplifier. The auxiliary control device mirrors the current of the output stage and then compares the mirrored current with a reference current to generate an auxiliary push/pull control signal, which is used to control the auxiliary output device. When the output signal is different from the input signal, the auxiliary control device turns on the auxiliary output device to provide an auxiliary output current for the output terminal. When the output signal is equal to the input signal, the auxiliary output device is turned off.

Abstract: The present invention discloses an apparatus for slew rate enhancement of an operational amplifier, wherein an auxiliary control device and an auxiliary output device are added to the output stage of an operational amplifier. The auxiliary control device mirrors the current of the output stage and then compares the mirrored current with a reference current to generate an auxiliary push/pull control signal, which is used to control the auxiliary output device. When the output signal is different from the input signal, the auxiliary control device turns on the auxiliary output device to provide an auxiliary output current for the output terminal. When the output signal is equal to the input signal, the auxiliary output device is turned off.