Abstract: The present invention relates to a security device for section processor which can execute an information security function of high speed data in an super highway information network in real time by implementing an information security algorithm by hardware in the section processor. According to the present invention, related hardware can be easily implemented by simply imbedding an encoder and a decoder in the section processor of the super highway information network. Thus, a section processor having information security functions can be easily implemented in one integrated circuit. Also, the security device for section processor in accordance with the present invention is superior to other device in terms of an information security function itself, economicity, efficiency, and power consumption efficiency.

Abstract: An apparatus for performing a modular multiplication, including a multiplicand register storing a multiplicand; a multiplier register storing a multiplier; a multiplier word counter counting the number of words of the multiplier register; a partial product calculator calculating a partial product for each word of an output of the multiplicand register and an output of the multiplier register; a first adder adding an output of the partial product calculator to an output of a left word shifter; a quotient estimation calculator estimating a quotient from an output of the first adder and an output of an N modular register; a multiplier multiplying an output of the 2N modular register from an output of the quotient estimation calculator; a multiplexer selecting one of an output of the multiplier and the output of the N modular register from an output of the multiplier word counter; a subtracter subtracting an output of the multiplexer from the output of the first adder; the left word shifter shifting an output of

Abstract: The present invention relates to a modular multiplication device for information security which needs only the hardware almost half as much as required in a conventional modular multiplication device wherein multiplication and division circuits are separately used, by performing a dual function of multiplication and division with a binary adder.

Abstract: A byte aligner and frame synchronizer for 622 Mbit/s high speed data includes a clock divider, a data width extension circuit, a byte alignment controller, a byte alignment circuit, a pattern selector, a continuous pattern detector, a frame pulse generator, a frame sync detector, a frame sync loss detector, and frame sync error detector, and performs byte alignment very fast while also stabilizing frame synchronization by reinforcing an error correction function.

Abstract: A frame synchronizing device for discriminating a time slot location for each channel of time-division multiplexed signals is disclosed. The frame synchronizing device according to the invention processes time-division multiplexed signals in parallel in a STM-4C(Synchronous Transport Module-4 Concatenation) of the Broadband Integrated Service Digital Network according to the ITU-T recommendation, such that the searching of frame synchronization can be achieved by detecting frame bytes on data being received at a high speed in the STM-4C structure to align the bytes based on the detected time interval, converting the frame data into the 8-bits parallel data and then detecting, in sequence, the frame bytes at a lower speed clock being divided by 8, thereby providing a simplified, less power consumptive frame synchronizing device in the STM-4C structure according to the ITU-T recommendation.

Abstract: A mobile communication method is disclosed, and particularly a power of two length pseudorandom noise sequence generator is disclosed, in which a pseudorandom noise code sequence is generated to use it for a direct sequence spreading of communication signals in a spread spectrum communication system. In the PN sequence generator, a mask value and a comparison value are calculated for shifting the PN sequence output having a length of 2.sup.N as much as wanted, so that the PN sequence can be shifted as much as a predetermined value in response to the single clock signal. In order to generate a PN sequence of the desired timing, a new PN mask value is directly obtained from the current PN mask value and the offset shift value to be shifted, and at the same time, a comparison value corresponding to the mask value is obtained, whereby ultimately a PN sequence having a length of 2.sup.N after shifting the cycle as much as the desired shifting value is obtained.