Patents by Inventor Chung Y. Yip

Chung Y. Yip has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Fast parity generator using complement pass-transistor logic
    Patent number: 5608741
    Abstract: The present invention discloses a fast parity bit generator using 4-bit XOR cells implemented using complement pass-transistor logic. For 2.sup.2n inputs, where n is an arbitrary positive integer, the parity bit is generated in n stages using only ##EQU1## 4-bit XOR cells. For 2.sup.2n+1 inputs, where n is an arbitrary positive integer, the parity bit is generated using ##EQU2## 4-bit XOR cells disposed in n rows and one 2-bit XOR cell disposed in the last row. The speed of operation of the XOR cells is further enhanced by using NMOS transistor logic within the XOR cells.
    Type: Grant
    Filed: November 23, 1993
    Date of Patent: March 4, 1997
    Assignee: Intel Corporation
    Inventors: Sudarshan Kumar, Shyue L. Kuo, Chung Y. Yip