Abstract: An input redundant circuit according to the present disclosure may include: a core power supply unit; a first input port connected to a first input voltage; a second input port connected to a second input voltage; a relay unit connected to the first input port and the second input port to supply one of the first input voltage and the second input voltage to the core power supply unit; and a surge current limiting unit coupled to the relay unit, configured to limit a surge current generated when the relay unit is switched between the first input voltage and the second input voltage.

Abstract: An input redundant circuit according to the present disclosure may include: a core power supply unit; a first input port connected to a first input voltage; a second input port connected to a second input voltage; a relay unit connected to the first input port and the second input port to supply one of the first input voltage and the second input voltage to the core power supply unit; and a surge current limiting unit coupled to the relay unit, configured to limit a surge current generated when the relay unit is switched between the first input voltage and the second input voltage.

Abstract: An input redundant circuit according to the present disclosure may include: a core power supply unit; a first input port connected to a first input voltage; a second input port connected to a second input voltage; a relay unit connected to the first input port and the second input port to supply one of the first input voltage and the second input voltage to the core power supply unit; and a surge current limiting unit coupled to the relay unit, configured to limit a surge current generated when the relay unit is switched between the first input voltage and the second input voltage.

Abstract: An input redundant circuit according to the present disclosure may include: a core power supply unit; a first input port connected to a first input voltage; a second input port connected to a second input voltage; a relay unit connected to the first input port and the second input port to supply one of the first input voltage and the second input voltage to the core power supply unit; and a surge current limiting unit coupled to the relay unit, configured to limit a surge current generated when the relay unit is switched between the first input voltage and the second input voltage.

Abstract: An input redundant circuit according to the present disclosure may include: a core power supply unit; a first input port connected to a first input voltage; a second input port connected to a second input voltage; a relay unit connected to the first input port and the second input port to supply one of the first input voltage and the second input voltage to the core power supply unit; and a surge current limiting unit coupled to the relay unit, configured to limit a surge current generated when the relay unit is switched between the first input voltage and the second input voltage.

Abstract: Embodiments of the present invention are directed to a metallization process for reducing the stress existing between the Al—Cu layer and the titanium nitride (TiN) layer, and solving the galvanic problem. The process does so by cooling the wafer in the vacuum apparatus where the metallization process is performed after formation of the Al—Cu layer and before the formation of the TiN layer. In accordance with an aspect of the present invention, a metallization process comprises placing a wafer in an Al—Cu sputtering chamber to form an Al—Cu layer on the wafer, and transferring the wafer to a titanium nitride sputtering chamber. An inert gas is introduced into the titanium nitride sputtering chamber to cool the wafer. A titanium nitride layer is formed on the Al—Cu layer of the wafer in the titanium nitride sputtering layer after cooling the wafer.

Abstract: Embodiments of the present invention are directed to a metallization process for reducing the stress existing between the Al—Cu layer and the titanium nitride (TiN) layer, and solving the galvanic problem. The process does so by cooling the wafer in the vacuum apparatus where the metallization process is performed after formation of the Al—Cu layer and before the formation of the TiN layer. In accordance with an aspect of the present invention, a metallization process comprises placing a wafer in an Al—Cu sputtering chamber to form an Al—Cu layer on the wafer, and transferring the wafer to a titanium nitride sputtering chamber. An inert gas is introduced into the titanium nitride sputtering chamber to cool the wafer. A titanium nitride layer is formed on the Al—Cu layer of the wafer in the titanium nitride sputtering layer after cooling the wafer.