Patents by Inventor Chung-Yang Wu

Chung-Yang Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8528195
    Abstract: A layout method for electronic components of a double-sided surface mount circuit board is presented, which includes the following steps. At least one first electronic component is fixed on a first side surface of a circuit board through a reflow soldering process. At least one second electronic component is inserted on the first side surface of the circuit board. The other first electronic component is placed on a second side surface of the circuit board, and the other second electronic component is inserted on the second side surface of the circuit board. Finally, a reflow soldering process is performed on the circuit board disposed with the first electronic components and the second electronic components, thereby completing a layout process for the electronic components on the two side surfaces of the circuit board at the same time.
    Type: Grant
    Filed: January 20, 2010
    Date of Patent: September 10, 2013
    Assignee: Inventec Corporation
    Inventors: Chung-Yang Wu, Hung-Tao Wong
  • Patent number: 8291370
    Abstract: A pad layout method for surface mount circuit board and a surface mount circuit board are described. The layout method includes the following steps. Firstly, coefficients of thermal expansion of a circuit board and a surface mounted component are obtained, and the circuit board is supplied with a plurality of predetermined layout positions in advance. Then, an operating temperature for combining the surface mounted component with the circuit board is determined, and a room temperature is measured. A plurality of actual layout positions on the circuit board is determined according to d=(CTEa?CTEb)×(Ts?Tr), where d is an offset distance between the actual layout position and the predetermined layout position. Finally, a plurality of pads is laid out on the actual layout positions, such that the pads are formed on the circuit board.
    Type: Grant
    Filed: January 19, 2010
    Date of Patent: October 16, 2012
    Assignee: Inventec Corporation
    Inventors: Chung-Yang Wu, Hung-Tao Wong
  • Publication number: 20120097440
    Abstract: A method for electronic component layout of a printed circuit board includes the following steps. First, a first solder joint is formed on a first surface of the printed circuit board. Then, an electronic component is clipped on a side edge of the printed circuit board in an installation direction. At this time, a first pin of the electronic component is placed on the first solder joint, and presses against a limiting portion of the first solder joint, and a second pin of the electronic component is placed on a second surface of the printed circuit board. Finally, a second solder joint is formed on the second surface, so that the second pin is fixed on the second solder joint and the first pin is fixed on the first solder joint.
    Type: Application
    Filed: February 2, 2011
    Publication date: April 26, 2012
    Applicant: INVENTEC CORPORATION
    Inventor: Chung Yang Wu
  • Publication number: 20120099260
    Abstract: A method of forming a ground structure suitable for electrical communication with a computer casing includes following steps of forming a ground layer on a surface of a circuit board, forming an insulating layer on the ground layer, and meanwhile forming at least one exposed surface at a part of the ground layer that is not covered by the insulating layer; and finally, covering at least one conductive layer on the exposed surface, in which the conductive layer is electrically coupled to the computer casing, so as to allow the computer casing to be electrically communicated with the ground layer. Since the conductive layer partially covers the exposed surface that is not covered by the insulating layer, and the exposed surface can further be formed when the insulating layer is formed, the additional fabrication cost of the circuit board is effectively reduced, and good electrostatic discharge protection effect is achieved.
    Type: Application
    Filed: January 20, 2011
    Publication date: April 26, 2012
    Applicant: INVENTEC CORPORATION
    Inventor: Chung Yang Wu
  • Publication number: 20110173808
    Abstract: A layout method for electronic components of a double-sided surface mount circuit board is presented, which includes the following steps. At least one first electronic component is fixed on a first side surface of a circuit board through a reflow soldering process. At least one second electronic component is inserted on the first side surface of the circuit board. The other first electronic component is placed on a second side surface of the circuit board, and the other second electronic component is inserted on the second side surface of the circuit board. Finally, a reflow soldering process is performed on the circuit board disposed with the first electronic components and the second electronic components, thereby completing a layout process for the electronic components on the two side surfaces of the circuit board at the same time.
    Type: Application
    Filed: January 20, 2010
    Publication date: July 21, 2011
    Applicant: INVENTEC CORPORATION
    Inventors: Chung-Yang Wu, Hung-Tao Wong
  • Publication number: 20110178623
    Abstract: A pad layout method for surface mount circuit board and a surface mount circuit board are described. The layout method includes the following steps. Firstly, coefficients of thermal expansion of a circuit board and a surface mounted component are obtained, and the circuit board is supplied with a plurality of predetermined layout positions in advance. Then, an operating temperature for combining the surface mounted component with the circuit board is determined, and a room temperature is measured. A plurality of actual layout positions on the circuit board is determined according to d=(CTEa?CTEb)×(Ts?Tr), where d is an offset distance between the actual layout position and the predetermined layout position. Finally, a plurality of pads is laid out on the actual layout positions, such that the pads are formed on the circuit board.
    Type: Application
    Filed: January 19, 2010
    Publication date: July 21, 2011
    Applicant: INVENTEC CORPORATION
    Inventors: Chung Yang Wu, Hung Tao Wong
  • Publication number: 20110157930
    Abstract: The power input stabilizing circuit provides a first resistor at the input terminals to suppress impulse current. Then, the power passes through a power input limiting circuit including a non-polarity capacitor, a rectifier circuit formed by diodes, and a polarity capacitor so as to provide a current within a specific range to a load. A constant current circuit including a third resistor, a diode, a fourth resistor, and a transistor is then employed to stabilize the load current. The performance and durability of the electrical or electronic appliance using the power input stabilizing circuit are therefore enhanced significantly.
    Type: Application
    Filed: December 31, 2009
    Publication date: June 30, 2011
    Inventors: Hui-Ming WU, Chung-Yang WU
  • Publication number: 20110024177
    Abstract: A method for soldering electronic components of a circuit board and a circuit board structure thereof are presented. The method includes providing a circuit board first; disposing at least one solder hole and at least one heat collecting hole on the circuit board, in which the heat collecting hole is disposed around the solder hole to form a heat collecting area; extending a pin of an electronic component into the solder hole; filling a solder within the solder hole through a soldering process; and keeping heat of the solder in the heat collecting area by the heat collecting hole. Thus, the pin of the electronic component within the solder hole is successfully combined with the solder.
    Type: Application
    Filed: July 29, 2009
    Publication date: February 3, 2011
    Applicant: Inventec Corporation
    Inventors: Hung Tao Wong, Chung Yang Wu
  • Publication number: 20090108418
    Abstract: A non-leaded semiconductor package structure is proposed, in which the structure of a lead frame is improved to let the lower surface of a die paddle of the lead frame be used to carry a die and the upper surface thereof be exposed out of the package structure. Moreover, a plurality of leads of the lead frame is located at the periphery of the lower surface of the die paddle. Each lead has an inner lead and an outer lead, and the outer lead is exposed out of the package structure. The package structure thus formed has a good heat-radiating effect and a reduced chance of leakage current.
    Type: Application
    Filed: October 29, 2007
    Publication date: April 30, 2009
    Inventors: Wa-Hua Wu, Szu-Chuan Pang, Chung-Yang Wu