Patents by Inventor Chung-Yen Chien

Chung-Yen Chien has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250133802
    Abstract: A semiconductor device includes a substrate having a first conductivity type and an epitaxial layer disposed on the substrate. A first trench and a second trench are disposed in the epitaxial layer. A first body region and a second body region both having a second conductivity type are disposed in the epitaxial layer, and located on two sides of the first trench, respectively. A first source region and a second source region both having the first conductivity type are disposed on the first body region and the second body region, respectively. A first electrode is disposed in the first trench. A source contact structure includes a first portion disposed in the first trench and is electrically connected to the first source region and the second source region. A first gate is disposed in the second trench.
    Type: Application
    Filed: October 23, 2023
    Publication date: April 24, 2025
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Sheng-Wei Fu, Chung-Yen Chien, Chung-Yeh Lee, Fu-Hsin Chen, Chen-Dong Tzou
  • Patent number: 10600906
    Abstract: A method for forming a semiconductor device is provided. A plurality of trenches are formed in the substrate. An isolation oxide layer is formed in the trenches and on the substrate. A shield polysilicon is deposited in the trenches and on the isolation oxide layer on the substrate. A first etching process is performed to remove a first portion of the shield polysilicon. A first removal process is performed to remove a first portion of the isolation oxide layer. A second etching process is performed to remove a second portion of the shield polysilicon. A second removal process is performed to remove a second portion of the isolation oxide layer. An inter-poly oxide layer is formed on the remaining shield polysilicon and the remaining isolation oxide layer, wherein the inter-poly oxide layer has a concave top surface.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: March 24, 2020
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Chung-Yen Chien, Sheng-Wei Fu, Chung-Yeh Lee
  • Publication number: 20200075758
    Abstract: A method for forming a semiconductor device is provided. A plurality of trenches are formed in the substrate. An isolation oxide layer is formed in the trenches and on the substrate. A shield polysilicon is deposited in the trenches and on the isolation oxide layer on the substrate. A first etching process is performed to remove a first portion of the shield polysilicon. A first removal process is performed to remove a first portion of the isolation oxide layer. A second etching process is performed to remove a second portion of the shield polysilicon. A second removal process is performed to remove a second portion of the isolation oxide layer. An inter-poly oxide layer is formed on the remaining shield polysilicon and the remaining isolation oxide layer, wherein the inter-poly oxide layer has a concave top surface.
    Type: Application
    Filed: November 7, 2019
    Publication date: March 5, 2020
    Applicant: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Chung-Yen CHIEN, Sheng-Wei FU, Chung-Yeh LEE
  • Publication number: 20190386132
    Abstract: A method for forming a semiconductor device is provided. A plurality of trenches are formed in the substrate. An isolation oxide layer is formed in the trenches and on the substrate. A shield polysilicon is deposited in the trenches and on the isolation oxide layer on the substrate. A first etching process is performed to remove a first portion of the shield polysilicon. A first removal process is performed to remove a first portion of the isolation oxide layer. A second etching process is performed to remove a second portion of the shield polysilicon. A second removal process is performed to remove a second portion of the isolation oxide layer. An inter-poly oxide layer is formed on the remaining shield polysilicon and the remaining isolation oxide layer, wherein the inter-poly oxide layer has a concave top surface.
    Type: Application
    Filed: June 13, 2018
    Publication date: December 19, 2019
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Chung-Yen CHIEN, Sheng-Wei FU, Chung-Yeh Lee
  • Patent number: 10510878
    Abstract: A method for forming a semiconductor device is provided. A plurality of trenches are formed in the substrate. An isolation oxide layer is formed in the trenches and on the substrate. A shield polysilicon is deposited in the trenches and on the isolation oxide layer on the substrate. A first etching process is performed to remove a first portion of the shield polysilicon. A first removal process is performed to remove a first portion of the isolation oxide layer. A second etching process is performed to remove a second portion of the shield polysilicon. A second removal process is performed to remove a second portion of the isolation oxide layer. An inter-poly oxide layer is formed on the remaining shield polysilicon and the remaining isolation oxide layer, wherein the inter-poly oxide layer has a concave top surface.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: December 17, 2019
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Chung-Yen Chien, Sheng-Wei Fu, Chung-Yeh Lee