Abstract: Semiconductor device structures having gate structures with tunable threshold voltages are provided. Various geometries of device structure can be varied to tune the threshold voltages. In some examples, distances from tops of fins to tops of gate structures can be varied to tune threshold voltages. In some examples, distances from outermost sidewalls of gate structures to respective nearest sidewalls of nearest fins to the respective outermost sidewalls (which respective gate structure overlies the nearest fin) can be varied to tune threshold voltages.

Abstract: An optical proximity correction (OPC) device and method is provided. The OPC device includes an analysis unit, a reverse pattern addition unit, a first OPC unit, a second OPC unit and an output unit. The analysis unit is configured to analyze a defect pattern from a photomask layout. The reverse pattern addition unit is configured to provide a reverse pattern within the defect pattern. The first OPC unit is configured to perform a first OPC procedure on whole of the photomask layout. The second OPC unit is configured to perform a second OPC procedure on the defect pattern of the photomask layout to enhance an exposure tolerance window. The output unit is configured to output the photomask layout which is corrected.

Abstract: A cryptographic Serial ATA (SATA) apparatus comprises a main controller, a SATA device protocol stack, a SATA host protocol stack, and a cryptographic engine. The cryptographic engine is operatively coupled between the main controller and the SATA device and host protocol stacks and configured to provide high-speed cryptographic processing.

Abstract: A cryptographic Serial ATA (SATA) apparatus comprises a main controller, a SATA device protocol stack, a SATA host protocol stack, and a cryptographic engine. The cryptographic engine is operatively coupled between the main controller and the SATA device and host protocol stacks and configured to provide high-speed cryptographic processing.

Abstract: A division technique unified quantizer-dequantizer circuit is disclosed. The unified quantizer-dequantizer includes a division circuit receiving a half step size q and an input signal x. The division circuit outputs a quantized coefficient signal y and a remainder R, where ##EQU1## The unified quantizer-dequantizer also includes a circuit receiving the quantized coefficient signal y, the remainder R, the half step size q and the input signal x.