Abstract: A package structure including a photonic, an electronic die, an encapsulant and a waveguide is provided. The photonic die includes an optical coupler. The electronic die is electrically coupled to the photonic die. The encapsulant laterally encapsulates the photonic die and the electronic die. The waveguide is disposed over the encapsulant and includes an upper surface facing away from the encapsulant. The waveguide includes a first end portion and a second end portion, the first end portion is optically coupled to the optical coupler, and the second end portion has a groove on the upper surface.

Abstract: Some embodiments relate to a thin film transistor comprising an active layer over a substrate. An insulator is stacked with the active layer. A gate electrode structure is stacked with the insulator and includes a gate material layer having a first work function and a first interfacial layer. The first interfacial layer is directly between the insulator and the gate material layer, wherein the gate electrode structure has a second work function that is different from the first work function.

Abstract: An integrated circuit package including electrically floating metal lines and a method of forming are provided. The integrated circuit package may include integrated circuit dies, an encapsulant around the integrated circuit dies, a redistribution structure on the encapsulant, a first electrically floating metal line disposed on the redistribution structure, a first electrical component connected to the redistribution structure, and an underfill between the first electrical component and the redistribution structure. A first opening in the underfill may expose a top surface of the first electrically floating metal line.

Abstract: A semiconductor device includes a gate, a semiconductor structure, a gate insulating layer, a first source/drain feature and a second source/drain feature. The gate insulating layer is located between the gate and the semiconductor structure. The semiconductor structure includes at least one first metal oxide layer, a first oxide layer, and at least one second metal oxide layer. The first oxide layer is located between the first metal oxide layer and the second metal oxide layer. The first source/drain feature and the second source/drain feature are electrically connected with the semiconductor structure.

Abstract: A package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler; an interconnect structure over the photonic layer; an electronic die and a first dielectric layer over the interconnect structure, where the electronic die is connected to the interconnect structure; a first substrate bonded to the electronic die and the first dielectric layer; a socket attached to a top surface of the first substrate; and a fiber holder coupled to the first substrate through the socket, where the fiber holder includes a prism that re-orients an optical path of an optical signal.

Abstract: Methods of manufacturing a semiconductor structure are provided. One of the methods includes: receiving a substrate including a first conductive region of a first transistor and a second conductive region of a second transistor, wherein the first transistor and the second transistor have different conductive types; performing an amorphization on the first conductive region and the second conductive region; performing an implantation over the first conductive region of the first transistor; forming a contact material layer over the first conductive region and the second conductive region; performing a thermal anneal on the first conductive region and the second conductive region; and performing a laser anneal on the first conductive region and the second conductive region.

Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.

Abstract: A semiconductor package including a first semiconductor die, a second semiconductor die, a first insulating encapsulation, a dielectric layer structure, a conductor structure and a second insulating encapsulation is provided. The first semiconductor die includes a first semiconductor substrate and a through silicon via (TSV) extending from a first side to a second side of the semiconductor substrate. The second semiconductor die is disposed on the first side of the semiconductor substrate. The first insulating encapsulation on the second semiconductor die encapsulates the first semiconductor die. A terminal of the TSV is coplanar with a surface of the first insulating encapsulation. The dielectric layer structure covers the first semiconductor die and the first insulating encapsulation. The conductor structure extends through the dielectric layer structure and contacts with the through silicon via.

Abstract: A thin film transistor includes a gate electrode embedded in an insulating layer that overlies a substrate, a gate dielectric overlying the gate electrode, an active layer comprising a compound semiconductor material and overlying the gate dielectric, and a source electrode and drain electrode contacting end portions of the active layer. The gate dielectric may have thicker portions over interfaces with the insulating layer to suppress hydrogen diffusion therethrough. Additionally or alternatively, a passivation capping dielectric including a dielectric metal oxide material may be interposed between the active layer and a dielectric layer overlying the active layer to suppress hydrogen diffusion therethrough.

Abstract: Some implementations described herein include systems and techniques for fabricating a wafer-on-wafer product using a filled lateral gap between beveled regions of wafers included in a stacked-wafer assembly and along a perimeter region of the stacked-wafer assembly. The systems and techniques include a deposition tool having an electrode with a protrusion that enhances an electromagnetic field along the perimeter region of the stacked-wafer assembly during a deposition operation performed by the deposition tool. Relative to an electromagnetic field generated by a deposition tool not including the electrode with the protrusion, the enhanced electromagnetic field improves the deposition operation so that a supporting fill material may be sufficiently deposited.

Abstract: A ferroelectric memory device and a semiconductor die are provided. The ferroelectric memory device includes a gate electrode; a channel layer, overlapped with the gate electrode; source/drain contacts, in contact with separate ends of the channel layer; a ferroelectric layer, lying between the gate electrode and the channel layer; and a first insertion layer, extending in between the ferroelectric layer and the channel layer, and comprising a metal carbonitride or a metal nitride.

Abstract: A semiconductor structure includes a die and a first connector. The first connector is disposed on the die. The first connector includes a first connecting housing, a first connecting element and a first connecting portion. The first connecting element is electrically connected to the die and disposed at a first side of the first connecting housing. The first connecting portion is disposed at a second side different from the first side of the first connecting housing, wherein the first connecting portion is one of a hole and a protrusion with respect to a surface of the second side of the first connecting housing.

Abstract: A manufacturing method of a semiconductor device includes at least the following steps. A sacrificial substrate is provided. An epitaxial layer is formed on the sacrificial substrate. An etch stop layer is formed on the epitaxial layer. Carbon atoms are implanted into the etch stop layer. A capping layer and a device layer are formed on the etch stop layer. A handle substrate is bonded to the device layer. The sacrificial substrate, the epitaxial layer, and the etch stop layer having the carbon atoms are removed from the handle substrate.

Abstract: A weighted end cap 30 for a golf club grip has a butt end 34 and an inner end 32 connected to a tubular portion 20. The butt end 34 has a weighted element 38 for movement of the center of gravity of the golf club grip.

Abstract: Hydrogen selective coatings, coated articles and methods for their formation and for hydrogen separation or purification. The coatings are formed by atomic layer deposition of suitable metal oxides with desirable hydrogen activation energy or hydrogen flux, e.g., silicon dioxide, and can be borne on a nonporous, thin-film metal or cermet substrate, e.g., a palladium sheet or layer. The coated substrate may include a porous support for the sheet or layer. The coated article may be used as a purification membrane and the coating can protect the metal layer from contaminants in the gas or process stream from which hydrogen is being purified. In some embodiments, the coated article can provide such protection at elevated temperatures in excess of 300° C.; and in other embodiments, can provide protection at temperatures in excess of 600° C. and even in excess of 800° C.

Abstract: Hydrogen selective coatings, coated articles and methods for their formation and for hydrogen separation or purification. The coatings are formed by atomic layer deposition of suitable metal oxides with desirable hydrogen activation energy or hydrogen flux, e.g., silicon dioxide, and can be borne on a nonporous, thin-film metal or cermet substrate, e.g., a palladium sheet or layer. The coated substrate may include a porous support for the sheet or layer. The coated article may be used as a purification membrane and the coating can protect the metal layer from contaminants in the gas or process stream from which hydrogen is being purified. In some embodiments, the coated article can provide such protection at elevated temperatures in excess of 300° C.; and in other embodiments, can provide protection at temperatures in excess of 600° C. and even in excess of 800° C.

Abstract: An electronic device includes a detection module, an identification code generation module, a decryption module, a comparison module, and a control module. The detection module transmits a detection signal after detecting that a power adapter is connected to the electronic device. The identification code generation module randomly generates an encrypted identification code after receiving the detection signal. The decryption module decrypts the identification code to generate a first decryption code. The comparison module compares a second decryption code that has been fed back from the power adapter after the power adapter receiving the detection signal, with the first decryption code. The control module controls the electronic device to receive power from the power adapter when the first decryption code is the same as the second decryption code.

Abstract: A thermoelectric heat pump (10) is provided including a thermoelectric array (30) having alternating P-type and N-type semiconductors (33, 34) and one or more water transport membranes (20).

Abstract: A heating and cooling system to maintain an area at a desired temperature including a thermoelectric device (102), a vapor compression system (106), and a control system (104) operably connected to the thermoelectric device (102) and the vapor compression system (106).

Abstract: A die defect inspecting system with a die defect inspecting function includes a wafer-positioning module, an image-capturing module, a die-sucking module, a die defect analyzing module, a die-classifying module and a control module. The image-capturing module is disposed beside one side of the wafer-positioning module in order to capture an image of each die. The die-sucking module is disposed above the wafer-positioning module and the image-capturing module in order to suck each die from the wafer-positioning module to a position above the image-capturing module for capturing a back image of a back surface of each die. The die defect analyzing module is electrically connected to the image-capturing module in order to judge whether the back image of the back surface of each die passes inspection standard.