Patents by Inventor Chung-Yi Wang
Chung-Yi Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250066793Abstract: Disclosed herein are novel single-stranded anti-sense oligonucleotides (ASOs) capable of reducing the transcription of thioredoxin domain containing protein 5 (TXNDC5) mRNA. Also disclosed is use of the single-stranded ASOs as disclosed herein for manufacturing medicaments suitable for treating a disease associated with upregulation of TXNDC5. Accordingly, a pharmaceutical composition comprising the disclosed ASO molecules is provided; as well as a method of treating a subject suffering from TXNDC5-mediated disease via administering to the subject the disclosed single-stranded ASO molecules.Type: ApplicationFiled: December 28, 2022Publication date: February 27, 2025Inventors: Ying-Shuan LAILEE, Chia-Wei LIU, Chi-Tang WANG, Pei-Yi TSAI, Chung-Hsiun WU, King LAM, Wei-Ting SUN, Kai-Chien YANG, Hung-Jyun HUANG
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Publication number: 20250057785Abstract: The present disclosure relates to use of 10?(Z), 13?(E), 15?(E)-Heptadecatrienyl hydroquinone compound (hereafter “HQ17(3)”) represented by the following Formula (12), a pharmaceutically acceptable salt, and/or a solvate and/or a hydrate thereof, and a pharmaceutical composition comprising the above compound, in treating coronavirus infection and diseases caused by the infection, especially SARS-COV-2 infection.Type: ApplicationFiled: October 31, 2023Publication date: February 20, 2025Inventors: MEI-HUI WANG, Kun-Liang LIN, Hung-Wen YU, Sui-Yuan CHANG, Chung-Yi HU, Shwu-Bin AU LIN
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Patent number: 12230712Abstract: A semiconductor device according to the present disclosure includes a dielectric fin having a helmet layer, a gate structure disposed over a first portion of the helmet layer and extending along a direction, and a dielectric layer adjacent the gate structure and disposed over a second portion of the helmet layer. A width of the first portion along the direction is greater than a width of the second portion along the direction.Type: GrantFiled: July 24, 2023Date of Patent: February 18, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Shan Lu, Chung-I Yang, Kuo-Yi Chao, Wen-Hsing Hsieh, Jiun-Ming Kuo, Chih-Ching Wang, Yuan-Ching Peng
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Patent number: 12230585Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. An alignment process is performed on a first semiconductor workpiece and a second semiconductor workpiece by virtue of a plurality of workpiece pins. The first semiconductor workpiece is bonded to the second semiconductor workpiece. A shift value is determined between the first and second semiconductor workpieces by virtue of a first plurality of alignment marks on the first semiconductor workpiece and a second plurality of alignment marks on the second semiconductor workpiece. A layer of an integrated circuit (IC) structure is formed over the second semiconductor workpiece based at least in part on the shift value.Type: GrantFiled: January 24, 2024Date of Patent: February 18, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yeong-Jyh Lin, Ching I Li, De-Yang Chiou, Sz-Fan Chen, Han-Jui Hu, Ching-Hung Wang, Ru-Liang Lee, Chung-Yi Yu
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Publication number: 20250038073Abstract: A package structure and a method for forming the same are provided. The package structure includes a first package structure and a second package structure. The first package structure includes a first device formed over a first substrate. The first device includes a first conductive plug connected to a through substrate via (TSV) structure formed in the first substrate. A buffer layer surrounds the first substrate. A first bonding layer is formed over the first substrate and the buffer layer. The second package structure includes a second device formed over a second substrate. A second bonding layer is formed over the second device. A hybrid bonding structure is between the first package structure and the second package structure by bonding the first bonding layer to the second bonding layer.Type: ApplicationFiled: July 27, 2023Publication date: January 30, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ke-Han SHEN, Chih-Yuan CHEN, Jiung WU, Hung-Yi Kuo, Chung-Ju LEE, Tung-He CHOU, Ji CUI, Kuo-Chung YEE, Chen-Hua YU, Cheng-Chieh HSIEH, Yu-Jen LIEN, Yian-Liang KUO, Shih-Hao TSENG, Jen Yu WANG, Tzu-Chieh Chou
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Patent number: 12211699Abstract: A method of removing a step height on a gate structure includes providing a substrate. A gate structure is disposed on the substrate. A dielectric layer covers the gate structure and the substrate. Then, a composite material layer is formed to cover the dielectric layer. Later, part of the composite material layer is removed to form a step height disposed directly on the gate structure. Subsequently, a wet etching is performed to remove the step height. After the step height is removed, the dielectric layer is etched to form a first contact hole to expose the gate structure.Type: GrantFiled: July 4, 2022Date of Patent: January 28, 2025Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yeh-Sheng Lin, Chang-Mao Wang, Chun-Chi Yu, Chung-Yi Chiu
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Patent number: 12142235Abstract: An apparatus including a pixel electrode circuit is provided. The pixel electrode circuit includes a first switch, a second switch, a first-type transistor, a first second-type transistor, and a second second-type transistor. The first switch and the second switch are respectively controlled by a first control signal and a second control signal. The first-type transistor includes a gate electrically connected to a first node, a first terminal connected to a first power supply voltage, and a second terminal connected to a third node. The first second-type transistor includes a gate electrically connected to a second node, a first terminal connected to a second power supply voltage, and a second terminal connected to the third node. The second second-type transistor includes a gate electrically connected to the second node, a first terminal being grounded, and a second terminal providing an output voltage.Type: GrantFiled: October 6, 2023Date of Patent: November 12, 2024Assignee: CYTESI INC.Inventors: Tung-Yu Wu, Chung-Yi Wang, Tang-Hung Po
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Patent number: 12073802Abstract: An apparatus including a pixel electrode circuit is provided. The pixel electrode circuit includes a first switch, a second switch, a first-type transistor, a first second-type transistor, and a second second-type transistor. The first switch and the second switch are respectively controlled by a first control signal and a second control signal. The first-type transistor includes a gate electrically connected to a first node, a first terminal connected to a first power supply voltage, and a second terminal connected to a third node. The first second-type transistor includes a gate electrically connected to a second node, a first terminal connected to a second power supply voltage, and a second terminal connected to the third node. The second second-type transistor includes a gate electrically connected to the second node, a first terminal being grounded, and a second terminal providing an output voltage.Type: GrantFiled: July 21, 2023Date of Patent: August 27, 2024Assignee: CYTESI, INC.Inventors: Tung-Yu Wu, Chung-Yi Wang, Tang-Hung Po
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Publication number: 20240165625Abstract: An apparatus and a system are provided. The system includes a top plate electrode, a dielectric layer, a plurality of pixel electrode circuits, and a plurality of detection circuits. A droplet is disposed between the top plate electrode and the dielectric layer. The plurality of pixel electrode circuits are arranged in a two-dimensional array. The pixel electrode circuits in each column of the two-dimensional array are electrically connected to a respective detection circuit of the plurality of detection circuits.Type: ApplicationFiled: November 15, 2023Publication date: May 23, 2024Inventors: Tung-Yu WU, Chung-Yi WANG, Tang-Hung PO
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Publication number: 20240169944Abstract: An apparatus including a pixel electrode circuit is provided. The pixel electrode circuit includes a first switch, a second switch, a first-type transistor, a first second-type transistor, and a second second-type transistor. The first switch and the second switch are respectively controlled by a first control signal and a second control signal. The first-type transistor includes a gate electrically connected to a first node, a first terminal connected to a first power supply voltage, and a second terminal connected to a third node. The first second-type transistor includes a gate electrically connected to a second node, a first terminal connected to a second power supply voltage, and a second terminal connected to the third node. The second second-type transistor includes a gate electrically connected to the second node, a first terminal being grounded, and a second terminal providing an output voltage.Type: ApplicationFiled: October 6, 2023Publication date: May 23, 2024Inventors: Tung-Yu WU, Chung-Yi WANG, Tang-Hung PO
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Publication number: 20240169943Abstract: An apparatus including a pixel electrode circuit is provided. The pixel electrode circuit includes a first switch, a second switch, a first-type transistor, a first second-type transistor, and a second second-type transistor. The first switch and the second switch are respectively controlled by a first control signal and a second control signal. The first-type transistor includes a gate electrically connected to a first node, a first terminal connected to a first power supply voltage, and a second terminal connected to a third node. The first second-type transistor includes a gate electrically connected to a second node, a first terminal connected to a second power supply voltage, and a second terminal connected to the third node. The second second-type transistor includes a gate electrically connected to the second node, a first terminal being grounded, and a second terminal providing an output voltage.Type: ApplicationFiled: July 21, 2023Publication date: May 23, 2024Inventors: Tung-Yu WU, Chung-Yi WANG, Tang-Hung PO
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Publication number: 20240159826Abstract: An automated test mechanism includes: preparing test software capable of reading and processing a file in a general form, and making the test software support N kinds of communication interfaces, M kinds of communication protocols, and multiple commands of K kinds of instruments, wherein the general form includes an interface setting part, a communication protocol setting part, and a function list part; creating multiple general form files in the general form to support the K kinds of instruments, wherein the multiple general form files include a first file and a second file that are prepared for a first instrument and a second instrument of the multiple instruments respectively; and when performing a first test with the first instrument, choosing the first file for the first test, and when performing a second test with the second instrument, choosing the second file for the second test.Type: ApplicationFiled: November 10, 2023Publication date: May 16, 2024Inventors: CHUNG-YI WANG, CHIA-CHE WU
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Publication number: 20240013353Abstract: A display apparatus is provided. The display apparatus includes a graphic processing unit, a display driver, and a display panel. The graphic processing unit is configured to provide a first image. The display driver is configured to correct an optical aberration of the first image to generate a second image. The display panel is configured to display the second image.Type: ApplicationFiled: May 25, 2023Publication date: January 11, 2024Applicant: HTC CorporationInventors: Sheng-Yan Lin, Chung-Yi Wang, Li-Wei Lin
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Publication number: 20230221543Abstract: A driving circuit for an electrowetting on dielectric (EWOD) pixel. The driving circuit includes a latch circuit for transmitting a source data pulse to a storage capacitor in response to an activation gate signal applied to the gate of the switch transistor and generating a latch voltage and an inversion circuit for outputting a driving voltage at either a first power voltage or a second power voltage based on the latch voltage generated by the latch circuit.Type: ApplicationFiled: January 3, 2023Publication date: July 13, 2023Inventors: Tung-Yu WU, Chung-Yi WANG, Tang-Hung PO
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Publication number: 20230191406Abstract: There is provided a heating device to independently and/or effectively heat the micro objects manipulated by a micro apparatus/system, for example the droplets of fluids in an electrowetting on dielectric EWOD device of a microfluidic apparatus. The heating device may include a plurality of micro heaters arranged in an array of rows and columns, and the micro heaters of the heating device may be disposed in relative to the electrode elements of the EWOD device, respectively. Therefore, the micro heaters of the heating device may heat one of the electrode elements of the EWOD device, thereby preventing thermal effect of the micro object on the other electrode elements.Type: ApplicationFiled: December 2, 2022Publication date: June 22, 2023Inventors: Tung-Yu WU, Tang-Hung PO, CHUNG-YI WANG
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Publication number: 20230123651Abstract: “An image sensing device is provided in the present invention. A control circuit determines a voltage change rate of a sensing signal according to a voltage value of the sensing signal generated by a light sensing unit during an estimation period, and controls an input adjustment circuit during an exposure period according to the voltage change rate to provide an input adjustment signal to a negative input end of an operational amplifier, such that a signal value of an amplified signal falls within a pre-set range during the exposure period.Type: ApplicationFiled: January 8, 2021Publication date: April 20, 2023Applicant: Egis Technology Inc.Inventors: Yu-Hsuan Lin, Tzu-Yang Peng, Chung-Yi Wang, Tzu-Li Hung
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Publication number: 20230115951Abstract: Provided is an electronic device comprising a touch display panel and an integrated chip. The touch display panel comprises a pixel array. The integrated chip is electrically connected to the pixel array. The integrated chip comprises a fingerprint sensing circuit and a display driving circuit. The fingerprint sensing circuit and the display driving circuit are electrically connected to multiple display data lines and sensing data lines through of the same pin. The multiple display data lines are respectively electrically connected to multiple color sub-pixels of the pixel array. The sensing data lines are electrically connected to multiple fingerprint sensing pixels of the pixel array. The multiple color sub-pixels are multiple liquid crystal display pixels.Type: ApplicationFiled: October 23, 2020Publication date: April 13, 2023Applicant: Egis Technology Inc.Inventors: Yu-Hsuan Lin, Yao-Li Huang, Chung-Yi Wang, Sheng Ruei Hsu
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Patent number: 11586321Abstract: An electronic device with fingerprint sensing function including a fingerprint sensing array, multiple fingerprint sensing signal readout lines, multiple touch driving lines, a touch driving circuit, and a read circuit is provided. The fingerprint sensing array includes multiple fingerprint sensing units arranged in array. The fingerprint sensing signal readout lines are respectively coupled to a column of fingerprint sensing units of the fingerprint sensing array. The touch driving lines are respectively interleaved with the fingerprint sensing signal readout lines. The touch driving circuit is coupled to the touch driving lines, and provides multiple touch driving signals to the touch driving lines. The read circuit is coupled to the fingerprint sensing signal readout lines. In response to the touch driving lines outputting the touch driving signals, the read circuit determines a touch position of a touch object based on multiple read signals output by the fingerprint sensing signal readout lines.Type: GrantFiled: March 11, 2020Date of Patent: February 21, 2023Assignee: Egis Technology Inc.Inventors: Chung-Yi Wang, Yu-Hsuan Lin
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Publication number: 20230043448Abstract: A detection circuit includes a first detection terminal, a second detection terminal, a first switch, a second switch, a first capacitor, a second capacitor and an amplifier. The first switch is coupled to the first detection terminal. The second switch is coupled to the second detection terminal. The first capacitor is coupled between the first switch and the second switch. The amplifier includes a first input terminal coupled to the second switch, a second input terminal used to receive an operation signal, and an output terminal used to output an output signal. The second capacitor is coupled between the first input terminal and the output terminal of the amplifier. The first switch and the second switch are turned on alternatively.Type: ApplicationFiled: August 19, 2020Publication date: February 9, 2023Applicant: Egis Technology Inc.Inventors: Chung-Yi Wang, Yu-Hsuan Lin, Tzu-Li Hung
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Publication number: 20230041756Abstract: A signal processing circuit includes a buffer, a first capacitor, a second capacitor, a first switch and a second switch. The buffer includes an input terminal for receiving an external signal and an output terminal for outputting an output signal. The first switch is coupled between the output terminal of the buffer and the first capacitor. The second switch is coupled between the output terminal of the buffer and the second capacitor. The first switch and the second switch are turned on alternately.Type: ApplicationFiled: August 12, 2020Publication date: February 9, 2023Applicant: Egis Technology Inc.Inventors: Chung-Yi Wang, Yu-Hsuan Lin, Tzu-Li Hung