Patents by Inventor Chung-Yu Chang

Chung-Yu Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250126933
    Abstract: A light emitting device including an epitaxial structure and a plurality of surface microstructures is provided. The epitaxial structure has a light emitting surface and a surrounding wall surface. The surrounding wall surface surrounds and is connected to the light emitting surface. The plurality of surface microstructures are separately arranged on the light emitting surface along a plurality of directions. The plurality of directions are not perpendicular to the surrounding wall surface. A light emitting device substrate including a plurality of the light emitting device is also provided.
    Type: Application
    Filed: November 13, 2023
    Publication date: April 17, 2025
    Applicant: PlayNitride Display Co., Ltd.
    Inventors: Yi-Min Su, Chung-Yu Chang, Yi-Ting Chen, Ching-Liang Lin
  • Publication number: 20220179468
    Abstract: In examples, a computer system comprises a first power supply having first and second power rails; a second power supply having a third power rail; a motherboard coupled to the first power rail; a central processing unit (CPU) coupled to the second power rail; a variable performance electronic component coupled to the third power rail; and a controller coupled to enable inputs of the first and second power supplies.
    Type: Application
    Filed: July 25, 2019
    Publication date: June 9, 2022
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventors: Chao-Wen Cheng, Chien-Fa Huang, Roger A. Pearson, Chung Yu Chang
  • Publication number: 20190313090
    Abstract: An intra prediction mode determining device includes: an intra prediction circuit, generating, according to a plurality of prediction modes, a plurality of sets of predicted pixel values of a target prediction unit by using a set of original pixel values of a neighbor prediction unit as a set of adjacent pixel values; a residual calculating circuit, calculating a plurality of residuals based on a set of the original pixel values and the plurality of sets of predicted pixel values of the target prediction unit; and a mode selecting circuit, selecting from the plurality of prediction modes one prediction mode as a candidate mode according to the plurality of sets of residuals.
    Type: Application
    Filed: September 25, 2018
    Publication date: October 10, 2019
    Inventors: Cheng-Yu HSIEH, Chung-Yu CHANG
  • Patent number: 7830203
    Abstract: A system-on-a-chip and a power gating circuit thereof are provided. The power gating circuit includes a first transistor, a charge pump circuit, and a hold circuit. A gate terminal of the first transistor is controlled by a first input signal. A first source/drain terminal of the first transistor is coupled to a first voltage. A second source/drain terminal of the first transistor outputs an output voltage. The charge pump circuit is coupled to a bulk terminal of the first transistor for changing a bulk voltage of the first transistor according to a second input signal. The hold circuit is coupled to the bulk terminal of the first transistor for holding the bulk voltage of the first transistor.
    Type: Grant
    Filed: December 25, 2007
    Date of Patent: November 9, 2010
    Assignee: Industrial Technology Research Institute
    Inventors: Chung-Yu Chang, Ching-Ji Huang
  • Publication number: 20090091372
    Abstract: A system-on-a-chip and a power gating circuit thereof are provided. The power gating circuit includes a first transistor, a charge pump circuit, and a hold circuit. A gate terminal of the first transistor is controlled by a first input signal. A first source/drain terminal of the first transistor is coupled to a first voltage. A second source/drain terminal of the first transistor outputs an output voltage. The charge pump circuit is coupled to a bulk terminal of the first transistor for changing a bulk voltage of the first transistor according to a second input signal. The hold circuit is coupled to the bulk terminal of the first transistor for holding the bulk voltage of the first transistor.
    Type: Application
    Filed: December 25, 2007
    Publication date: April 9, 2009
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chung-Yu Chang, Ching-Ji Huang
  • Patent number: 7496464
    Abstract: A validation system includes: a source agent for storing a plurality of test patterns; a drain agent for performing a validation operation according to a test result; and a device under test (DUT). The device under test includes: a first interface electrically connected to the source agent for communicating with the source agent and receiving the test patterns outputted from the source agent; a target system electrically connected to the first interface for processing the test patterns to generate a plurality of test results; and a second interface electrically connected to the target system and the drain agent for communicating with the drain agent and transferring the plurality of test results to the drain agent.
    Type: Grant
    Filed: March 21, 2006
    Date of Patent: February 24, 2009
    Assignee: Mediatek USA Inc.
    Inventors: Chien-Chung Huang, Yuan-Liang Cheng, Tung-Hao Huang, You-Min Yeh, Chung-Yu Chang
  • Patent number: 7383259
    Abstract: A system for merging product characterization information with a characterized product employs a merging rule database and a product characterization database. A merging processor receives the product characterization information and the merging criteria to create a characterization information result. The characterization information result is created by extracting a trigger merging rule form the merging rule database and determining whether the trigger merging rule has been met to initiate merging the product characterization information with the product. If the products have no characterizations that meet the merging criteria, a union map and an intersection map for the characterized product are created. The merged product characterization information is connected to the product by marking the product to identify it as having met the merging criteria.
    Type: Grant
    Filed: June 4, 2004
    Date of Patent: June 3, 2008
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Keng-Chia Yang, Chiu Wen Jen, Chung-Yu Chang, Kuo-Rung Hsiao
  • Publication number: 20070225826
    Abstract: A validation system includes: a source agent for storing a plurality of test patterns; a drain agent for performing a validation operation according to a test result; and a device under test (DUT). The device under test includes: a first interface electrically connected to the source agent for communicating with the source agent and receiving the test patterns outputted from the source agent; a target system electrically connected to the first interface for processing the test patterns to generate a plurality of test results; and a second interface electrically connected to the target system and the drain agent for communicating with the drain agent and transferring the plurality of test results to the drain agent.
    Type: Application
    Filed: March 21, 2006
    Publication date: September 27, 2007
    Inventors: Chien-Chung Huang, Yuan-Liang Cheng, Tung-Hao Huang, You-Min Yeh, Chung-Yu Chang
  • Publication number: 20050278329
    Abstract: A system for merging product characterization information with a characterized product employs a merging rule database and a product characterization database. A merging processor receives the product characterization information and the merging criteria to create a characterization information result. The characterization information result is created by extracting a trigger merging rule form the merging rule database and determining whether the trigger merging rule has been met to initiate merging the product characterization information with the product. If the products have no characterizations that meet the merging criteria, a union map and an intersection map for the characterized product are created. The merged product characterization information is connected to the product by marking the product to identify it as having met the merging criteria.
    Type: Application
    Filed: June 4, 2004
    Publication date: December 15, 2005
    Inventors: Keng-Chia Yang, Chiu Wen Jen, Chung-Yu Chang, Kuo-Rung Hsiao
  • Patent number: 5777078
    Abstract: An inactive pore-forming agent which is activated to lytic function by a condition such as pH, light, heat, reducing potential, or metal ion concentration, or substance such as a protease, at the surface of a cell.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: July 7, 1998
    Assignee: Worcester Foundation for Experimental Biology
    Inventors: Hagan Bayley, Barbara J. Walker, Chung-yu Chang, Brett Niblack, Rekha Panchal