Patents by Inventor Chung-Yu Chang
Chung-Yu Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11968856Abstract: Exemplary subpixel structures include a directional light-emitting diode structure characterized by a full-width-half-maximum (FWHM) of emitted light having a divergence angle of less than or about 10°. The subpixel structure further includes a lens positioned a first distance from the light-emitting diode structure, where the lens is shaped to focus the emitted light from the light-emitting diode structure. The subpixel structure still further includes a patterned light absorption barrier positioned a second distance from the lens. The patterned light absorption barrier defines an opening in the barrier, and the focal point of the light focused by the lens is positioned within the opening. The subpixels structures may be incorporated into a pixel structure, and pixel structures may be incorporated into a display that is free of a polarizer layer.Type: GrantFiled: October 4, 2021Date of Patent: April 23, 2024Assignee: Applied Materials, Inc.Inventors: Chung-Chih Wu, Po-Jui Chen, Hoang Yan Lin, Guo-Dong Su, Wei-Kai Lee, Chi-Jui Chang, Wan-Yu Lin, Byung Sung Kwak, Robert Jan Visser
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Publication number: 20240116707Abstract: A powered industrial truck includes a lateral movement assembly including four sliding members and four pivotal members both on a wheeled carriage, four links having a first end pivotably secured to the sliding member and a second end pivotably secured to either end of the pivotal member, a motor shaft having two ends pivotably secured to the pivotal members respectively, a first electric motor on one frame member, and four mounts attached to the sliding members respectively; two lift assemblies including a second electric motor, a shaft having two ends rotatably secured to the sliding members respectively, two gear trains at the ends of the shaft respectively, a first gear connected to the second electric motor, a second gear on the shaft, and a first roller chain on the first and second gears; two electric attachments on the platform and being laterally moveable, each attachment. The mount has rollers.Type: ApplicationFiled: September 21, 2023Publication date: April 11, 2024Inventors: Jung-Chieh Chang, Yi-Sheng Chen, Jen-Yung Hsiao, Chia-Fu Hsiao, Wei-Qi Lao, Chen-Chih Chan, Chung-Yu Liu
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Patent number: 11956994Abstract: The present disclosure is generally related to 3D imaging capable OLED displays. A light field display comprises an array of 3D light field pixels, each of which comprises an array of corrugated OLED pixels, a metasurface layer disposed adjacent to the array of 3D light field pixels, and a plurality of median layers disposed between the metasurface layer and the corrugated OLED pixels. Each of the corrugated OLED pixels comprises primary or non-primary color subpixels, and produces a different view of an image through the median layers to the metasurface to form a 3D image. The corrugated OLED pixels combined with a cavity effect reduce a divergence of emitted light to enable effective beam direction manipulation by the metasurface. The metasurface having a higher refractive index and a smaller filling factor enables the deflection and direction of the emitted light from the corrugated OLED pixels to be well controlled.Type: GrantFiled: August 10, 2021Date of Patent: April 9, 2024Assignee: Applied Materials, Inc.Inventors: Chung-Chih Wu, Hoang Yan Lin, Guo-Dong Su, Zih-Rou Cyue, Li-Yu Yu, Wei-Kai Lee, Guan-Yu Chen, Chung-Chia Chen, Wan-Yu Lin, Gang Yu, Byung-Sung Kwak, Robert Jan Visser, Chi-Jui Chang
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Patent number: 11915994Abstract: A package structure is provided. The package structure includes a semiconductor die and a thermoelectric structure disposed on the semiconductor die. The thermoelectric structure includes P-type semiconductor blocks, N-type semiconductor blocks and metal pads. The P-type semiconductor blocks and the N-type semiconductor blocks are arranged in alternation with the metal pads connecting the P-type semiconductor blocks and the N-type semiconductor blocks. When a current flowing through one of the N-type semiconductor block, one of the metal pad, and one of the P-type semiconductor block in order, the metal pad between the N-type semiconductor block and the P-type semiconductor block forms a cold junction which absorbs heat generated by the semiconductor die.Type: GrantFiled: August 12, 2021Date of Patent: February 27, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Yen Hsieh, Chih-Horng Chang, Chung-Yu Lu
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Publication number: 20220179468Abstract: In examples, a computer system comprises a first power supply having first and second power rails; a second power supply having a third power rail; a motherboard coupled to the first power rail; a central processing unit (CPU) coupled to the second power rail; a variable performance electronic component coupled to the third power rail; and a controller coupled to enable inputs of the first and second power supplies.Type: ApplicationFiled: July 25, 2019Publication date: June 9, 2022Applicant: Hewlett-Packard Development Company, L.P.Inventors: Chao-Wen Cheng, Chien-Fa Huang, Roger A. Pearson, Chung Yu Chang
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Publication number: 20190313090Abstract: An intra prediction mode determining device includes: an intra prediction circuit, generating, according to a plurality of prediction modes, a plurality of sets of predicted pixel values of a target prediction unit by using a set of original pixel values of a neighbor prediction unit as a set of adjacent pixel values; a residual calculating circuit, calculating a plurality of residuals based on a set of the original pixel values and the plurality of sets of predicted pixel values of the target prediction unit; and a mode selecting circuit, selecting from the plurality of prediction modes one prediction mode as a candidate mode according to the plurality of sets of residuals.Type: ApplicationFiled: September 25, 2018Publication date: October 10, 2019Inventors: Cheng-Yu HSIEH, Chung-Yu CHANG
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Patent number: 7830203Abstract: A system-on-a-chip and a power gating circuit thereof are provided. The power gating circuit includes a first transistor, a charge pump circuit, and a hold circuit. A gate terminal of the first transistor is controlled by a first input signal. A first source/drain terminal of the first transistor is coupled to a first voltage. A second source/drain terminal of the first transistor outputs an output voltage. The charge pump circuit is coupled to a bulk terminal of the first transistor for changing a bulk voltage of the first transistor according to a second input signal. The hold circuit is coupled to the bulk terminal of the first transistor for holding the bulk voltage of the first transistor.Type: GrantFiled: December 25, 2007Date of Patent: November 9, 2010Assignee: Industrial Technology Research InstituteInventors: Chung-Yu Chang, Ching-Ji Huang
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Publication number: 20090091372Abstract: A system-on-a-chip and a power gating circuit thereof are provided. The power gating circuit includes a first transistor, a charge pump circuit, and a hold circuit. A gate terminal of the first transistor is controlled by a first input signal. A first source/drain terminal of the first transistor is coupled to a first voltage. A second source/drain terminal of the first transistor outputs an output voltage. The charge pump circuit is coupled to a bulk terminal of the first transistor for changing a bulk voltage of the first transistor according to a second input signal. The hold circuit is coupled to the bulk terminal of the first transistor for holding the bulk voltage of the first transistor.Type: ApplicationFiled: December 25, 2007Publication date: April 9, 2009Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Chung-Yu Chang, Ching-Ji Huang
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Patent number: 7496464Abstract: A validation system includes: a source agent for storing a plurality of test patterns; a drain agent for performing a validation operation according to a test result; and a device under test (DUT). The device under test includes: a first interface electrically connected to the source agent for communicating with the source agent and receiving the test patterns outputted from the source agent; a target system electrically connected to the first interface for processing the test patterns to generate a plurality of test results; and a second interface electrically connected to the target system and the drain agent for communicating with the drain agent and transferring the plurality of test results to the drain agent.Type: GrantFiled: March 21, 2006Date of Patent: February 24, 2009Assignee: Mediatek USA Inc.Inventors: Chien-Chung Huang, Yuan-Liang Cheng, Tung-Hao Huang, You-Min Yeh, Chung-Yu Chang
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Patent number: 7383259Abstract: A system for merging product characterization information with a characterized product employs a merging rule database and a product characterization database. A merging processor receives the product characterization information and the merging criteria to create a characterization information result. The characterization information result is created by extracting a trigger merging rule form the merging rule database and determining whether the trigger merging rule has been met to initiate merging the product characterization information with the product. If the products have no characterizations that meet the merging criteria, a union map and an intersection map for the characterized product are created. The merged product characterization information is connected to the product by marking the product to identify it as having met the merging criteria.Type: GrantFiled: June 4, 2004Date of Patent: June 3, 2008Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Keng-Chia Yang, Chiu Wen Jen, Chung-Yu Chang, Kuo-Rung Hsiao
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Publication number: 20070225826Abstract: A validation system includes: a source agent for storing a plurality of test patterns; a drain agent for performing a validation operation according to a test result; and a device under test (DUT). The device under test includes: a first interface electrically connected to the source agent for communicating with the source agent and receiving the test patterns outputted from the source agent; a target system electrically connected to the first interface for processing the test patterns to generate a plurality of test results; and a second interface electrically connected to the target system and the drain agent for communicating with the drain agent and transferring the plurality of test results to the drain agent.Type: ApplicationFiled: March 21, 2006Publication date: September 27, 2007Inventors: Chien-Chung Huang, Yuan-Liang Cheng, Tung-Hao Huang, You-Min Yeh, Chung-Yu Chang
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Publication number: 20050278329Abstract: A system for merging product characterization information with a characterized product employs a merging rule database and a product characterization database. A merging processor receives the product characterization information and the merging criteria to create a characterization information result. The characterization information result is created by extracting a trigger merging rule form the merging rule database and determining whether the trigger merging rule has been met to initiate merging the product characterization information with the product. If the products have no characterizations that meet the merging criteria, a union map and an intersection map for the characterized product are created. The merged product characterization information is connected to the product by marking the product to identify it as having met the merging criteria.Type: ApplicationFiled: June 4, 2004Publication date: December 15, 2005Inventors: Keng-Chia Yang, Chiu Wen Jen, Chung-Yu Chang, Kuo-Rung Hsiao
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Patent number: 5777078Abstract: An inactive pore-forming agent which is activated to lytic function by a condition such as pH, light, heat, reducing potential, or metal ion concentration, or substance such as a protease, at the surface of a cell.Type: GrantFiled: June 7, 1995Date of Patent: July 7, 1998Assignee: Worcester Foundation for Experimental BiologyInventors: Hagan Bayley, Barbara J. Walker, Chung-yu Chang, Brett Niblack, Rekha Panchal