Patents by Inventor Chung-Yu Chiang

Chung-Yu Chiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12243871
    Abstract: Examples of an integrated circuit with a capacitor structure and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a substrate and a trench isolation material disposed on the substrate. An isolation structure is disposed on the trench isolation material. A first electrode disposed on the isolation structure, and a second electrode disposed on the isolation structure. A capacitor dielectric is disposed on the isolation structure between the first electrode and the second electrode. In some such examples, the isolation structure includes a first hard mask disposed on the trench isolation material, a dielectric disposed on the first hard mask, and a second hard mask disposed on the dielectric.
    Type: Grant
    Filed: February 20, 2023
    Date of Patent: March 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsiao-Han Liu, Hoppy Lee, Chung-Yu Chiang, Po-Nien Chen, Chih-Yung Lin
  • Publication number: 20240105849
    Abstract: A method for forming a semiconductor structure is provided. The method for forming the semiconductor structure includes forming a fin structure over a substrate in a first direction, forming a first gate stack, a second gate stack and a third gate stack across the fin structure, removing the first gate stack to form a trench, depositing a cutting structure in the trench, and forming a first contact plug between the cutting structure and the second gate stack and a second contact plug between the second gate stack and the third gate stack. The fin structure is cut into two segments by the trench. A first dimension of the first contact plug in the first direction is greater than a second dimension of the second contact plug in the first direction.
    Type: Application
    Filed: February 10, 2023
    Publication date: March 28, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Da-Zhi ZHANG, Chun-An LU, Chung-Yu CHIANG, Po-Nien CHEN, Hsiao-Han LIU, Jhon-Jhy LIAW, Chih-Yung LIN
  • Publication number: 20240105775
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first source/drain structure and a second source/drain structure over and in a substrate. The method includes forming a first gate stack, a second gate stack, a third gate stack, and a fourth gate stack over the substrate. Each of the first gate stack or the second gate stack is wider than each of the third gate stack or the fourth gate stack. The method includes forming a first contact structure and a second contact structure over the first source/drain structure and the second source/drain structure respectively. A first average width of the first contact structure is substantially equal to a second average width of the second contact structure.
    Type: Application
    Filed: February 9, 2023
    Publication date: March 28, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Yu CHIANG, Hsiao-Han LIU, Yuan-Hung TSENG, Chih-Yung LIN
  • Publication number: 20230207320
    Abstract: Examples of an integrated circuit with a capacitor structure and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a substrate and a trench isolation material disposed on the substrate. An isolation structure is disposed on the trench isolation material. A first electrode disposed on the isolation structure, and a second electrode disposed on the isolation structure. A capacitor dielectric is disposed on the isolation structure between the first electrode and the second electrode. In some such examples, the isolation structure includes a first hard mask disposed on the trench isolation material, a dielectric disposed on the first hard mask, and a second hard mask disposed on the dielectric.
    Type: Application
    Filed: February 20, 2023
    Publication date: June 29, 2023
    Inventors: Hsiao-Han Liu, Hoppy Lee, Chung-Yu Chiang, Po-Nien Chen, Chih-Yung Lin
  • Patent number: 11587790
    Abstract: Examples of an integrated circuit with a capacitor structure and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a substrate and a trench isolation material disposed on the substrate. An isolation structure is disposed on the trench isolation material. A first electrode disposed on the isolation structure, and a second electrode disposed on the isolation structure. A capacitor dielectric is disposed on the isolation structure between the first electrode and the second electrode. In some such examples, the isolation structure includes a first hard mask disposed on the trench isolation material, a dielectric disposed on the first hard mask, and a second hard mask disposed on the dielectric.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: February 21, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsiao-Han Liu, Hoppy Lee, Chung-Yu Chiang, Po-Nien Chen, Chih-Yung Lin
  • Publication number: 20210091172
    Abstract: Examples of an integrated circuit with a capacitor structure and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a substrate and a trench isolation material disposed on the substrate. An isolation structure is disposed on the trench isolation material. A first electrode disposed on the isolation structure, and a second electrode disposed on the isolation structure. A capacitor dielectric is disposed on the isolation structure between the first electrode and the second electrode. In some such examples, the isolation structure includes a first hard mask disposed on the trench isolation material, a dielectric disposed on the first hard mask, and a second hard mask disposed on the dielectric.
    Type: Application
    Filed: December 7, 2020
    Publication date: March 25, 2021
    Inventors: Hsiao-Han Liu, Hoppy Lee, Chung-Yu Chiang, Po-Nien Chen, Chih-Yung Lin
  • Patent number: 10861928
    Abstract: Examples of an integrated circuit with a capacitor structure and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a substrate and a trench isolation material disposed on the substrate. An isolation structure is disposed on the trench isolation material. A first electrode disposed on the isolation structure, and a second electrode disposed on the isolation structure. A capacitor dielectric is disposed on the isolation structure between the first electrode and the second electrode. In some such examples, the isolation structure includes a first hard mask disposed on the trench isolation material, a dielectric disposed on the first hard mask, and a second hard mask disposed on the dielectric.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: December 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsiao-Han Liu, Hoppy Lee, Chung-Yu Chiang, Po-Nien Chen, Chih-Yung Lin
  • Publication number: 20200091277
    Abstract: Examples of an integrated circuit with a capacitor structure and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a substrate and a trench isolation material disposed on the substrate. An isolation structure is disposed on the trench isolation material. A first electrode disposed on the isolation structure, and a second electrode disposed on the isolation structure. A capacitor dielectric is disposed on the isolation structure between the first electrode and the second electrode. In some such examples, the isolation structure includes a first hard mask disposed on the trench isolation material, a dielectric disposed on the first hard mask, and a second hard mask disposed on the dielectric.
    Type: Application
    Filed: November 7, 2018
    Publication date: March 19, 2020
    Inventors: Hsiao-Han Liu, Hoppy Lee, Chung-Yu Chiang, Po-Nien Chen, Chih-Yung Lin
  • Patent number: 8283734
    Abstract: An integrated circuit device and method for manufacturing the integrated circuit device are disclosed. An exemplary method includes providing a substrate; forming a first gate over the substrate for a first device having a first threshold voltage characteristic, the first gate including a first material having a first-type work function; forming a second gate over the substrate for a second device having a second threshold voltage characteristic that is greater than the first threshold voltage characteristic, the second gate including a second material having a second-type work function that is opposite the first-type work function; and configuring the first device and the second device as a same channel type device.
    Type: Grant
    Filed: April 9, 2010
    Date of Patent: October 9, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Yu Chiang, Da-Wen Lin, Shyh-Wei Wang
  • Publication number: 20110248351
    Abstract: An integrated circuit device and method for manufacturing the integrated circuit device are disclosed. An exemplary method includes providing a substrate; forming a first gate over the substrate for a first device having a first threshold voltage characteristic, the first gate including a first material having a first-type work function; forming a second gate over the substrate for a second device having a second threshold voltage characteristic that is greater than the first threshold voltage characteristic, the second gate including a second material having a second-type work function that is opposite the first-type work function; and configuring the first device and the second device as a same channel type device.
    Type: Application
    Filed: April 9, 2010
    Publication date: October 13, 2011
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Yu Chiang, Da-Wen Lin, Shyh-Wei Wang