Patents by Inventor Chung-Yu Lu

Chung-Yu Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210327723
    Abstract: One embodiment includes partially forming a first through via in a substrate of an interposer, the first through via extending into a first side of the substrate of the interposer. The method also includes bonding a first die to the first side of the substrate of the interposer. The method also includes recessing a second side of the substrate of the interposer to expose the first through via, the first through via protruding from the second side of the substrate of the interposer, where after the recessing, the substrate of the interposer is less than 50 ?m thick. The method also includes and forming a first set of conductive bumps on the second side of the substrate of the interposer, at least one of the first set of conductive bumps being electrically coupled to the exposed first through via.
    Type: Application
    Filed: October 7, 2020
    Publication date: October 21, 2021
    Inventors: Chung-Yu Lu, Ping-Kang Huang, Sao-Ling Chiu, Shang-Yun Hou
  • Publication number: 20210233863
    Abstract: Method for fabricating a semiconductor structure is provided. First features are formed in a first product region of each die area and in a material layer through a first mask. Second features are formed in a second product region of each die area and in the material layer through a second mask. Third features are formed in a third product region of each die area and in the material layer through a third mask. Fourth features are formed in a fourth product region of each die area and in the material layer through a fourth mask. Fifth features are formed in an alignment region between the first, second, third and fourth product regions of each die area and in the material layer through the first, second, third and fourth masks. The first product region is free of the second, third, and fourth features.
    Type: Application
    Filed: April 9, 2021
    Publication date: July 29, 2021
    Inventors: Chung-Yu LU, Yao-Jen CHANG, Sao-Ling CHIU
  • Patent number: 10978404
    Abstract: Method for fabricating a semiconductor structure is provided. First features are formed in a first product region of each die area in a material layer through a first mask. Second features are formed in a second product region of each die area in the material layer through a second mask. Third features are formed in a third product region of each die area in the material layer through a third mask. Fourth features are formed in a fourth product region of each die area in the material layer through a fourth mask. Fifth features are formed in an alignment region of each die area in the material layer through the first through fourth masks. The first product region is adjacent to and in physical contact with the second and third product regions, and the first product region is free of the second, third, and fourth features.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: April 13, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chung-Yu Lu, Yao-Jen Chang, Sao-Ling Chiu
  • Publication number: 20210057350
    Abstract: Method for fabricating a semiconductor structure is provided. First features are formed in a first product region of each die area in a material layer through a first mask. Second features are formed in a second product region of each die area in the material layer through a second mask. Third features are formed in a third product region of each die area in the material layer through a third mask. Fourth features are formed in a fourth product region of each die area in the material layer through a fourth mask. Fifth features are formed in an alignment region of each die area in the material layer through the first through fourth masks. The first product region is adjacent to and in physical contact with the second and third product regions, and the first product region is free of the second, third, and fourth features.
    Type: Application
    Filed: August 22, 2019
    Publication date: February 25, 2021
    Inventors: Chung-Yu LU, Yao-Jen CHANG, Sao-Ling CHIU
  • Publication number: 20200312770
    Abstract: Board substrates, three-dimensional integrated circuit structures and methods of forming the same are disclosed. A board substrate includes a core layer, a first build-up layer, a second build-up layer, a first group of bumps, a second first group of bumps and at least one first underfill blocking wall. The first build-up layer and the second build-up layer are disposed on opposite sides of the core layer. The first group of bumps is disposed over the first build-up layer. The second first group of bumps is disposed over the first build-up layer. The at least one first underfill blocking wall is disposed over the first build-up layer and between the first group of bumps and the second group of bumps.
    Type: Application
    Filed: September 5, 2019
    Publication date: October 1, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Yu Lu, Ping-Kang Huang, Sao-Ling Chiu
  • Patent number: 10262939
    Abstract: Various structures having a fuse and methods for forming those structures are described. An embodiment is a method. The method comprises attaching a first die to a first side of a component using first electrical connectors. After the attaching, at least one of (i) the first die comprises a first fuse, (ii) the first side of the component comprises a second fuse, (iii) a second side of the component comprises a third fuse, the second side being opposite the first side, or (iv) a combination thereof. The method further comprises after the attaching the first die to the first side of the component, blowing the first fuse, the second fuse, the third fuse, or a combination thereof.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: April 16, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Yu Lu, Hsien-Pin Hu, Shin-Puu Jeng, Shang-Yun Hou, Tzuan-Horng Liu, Shih-Wen Huang, Chun Hua Chang
  • Patent number: 9978637
    Abstract: Various embodiments of mechanisms for forming through a three-dimensional integrated circuit (3DIC) structure are provided. The 3DIC structure includes an interposer bonded to a die and a substrate. The interposer has a conductive structure with through silicon vias (TSVs) connected to a patterned metal pad and a conductive structure on opposite ends of the TSVs. The pattern metal pad is embedded with dielectric structures to reduce dishing effect and has regions over TSVs that are free of the dielectric structures. The conductive structure has 2 or more TSVs. By using a patterned metal pad and 2 or more TSVs, the reliability and yield of the conductive structure and the 3DIC structure are improved.
    Type: Grant
    Filed: October 11, 2013
    Date of Patent: May 22, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzuan-Horng Liu, Shih-Wen Huang, Chung-Yu Lu, Hsien-Pin Hu, Shang-Yun Hou, Shin-Puu Jeng
  • Patent number: 9882240
    Abstract: A graft copolymer comprising a backbone polymer and a branched-chain polymer, and represented by formula (I), where A, B, Ra, Rb, Rc, Rd, Re, Rf, G1, G2, G3, G4, Y1, Y2, and k are as defined in the specification. A process for producing the grate copolymer, a process for preparing a gel polymer electrolyte including the graft copolymer, and an intermediate copolymer of the graft copolymer are also disclosed.
    Type: Grant
    Filed: August 11, 2014
    Date of Patent: January 30, 2018
    Assignee: NATIONAL CHENG KUNG UNIVERSITY
    Inventors: Ping-Lin Kuo, Sheng-Shu Hou, Chung-Yu Lu, Ching-An Wu, Chih-Hao Tsao, Chun-Han Hsu
  • Patent number: 9653531
    Abstract: A method of manufacturing a package may include: providing a first device having a first redistribution layer (RDL) and an insulator layer disposed over the first RDL; and forming a first micro-bump line over the insulator layer of the first device. The first micro-bump line may extend laterally over a surface of the insulator layer facing away from the first RDL, and a first inductor of the package comprises the first RDL and the first micro-bump line.
    Type: Grant
    Filed: October 14, 2014
    Date of Patent: May 16, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiao-Tsung Yen, Min-Chie Jeng, Hsien-Pin Hu, Tzuan-Horng Liu, Chin-Wei Kuo, Chung-Yu Lu, Yu-Ling Lin
  • Patent number: 9627223
    Abstract: Methods and apparatus for forming a semiconductor device package on an interposer using a micro-bump layer are disclosed. The micro-bump layer may comprise micro-bumps and micro-bump lines, where a micro-bump is used as a vertical connection between a die and the interposer, and a micro-bump line is used as a horizontal connection for signal transmission between different dies above the interposer. The micro-bump lines may be formed at the same time as the formation of the micro-bumps with little or no additional cost.
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: April 18, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Yu Lu, Hsien-Pin Hu, Hsiao-Tsung Yen, Tzuan-Horng Liu, Shih-Wen Huang, Shang-Yun Hou, Shin-Puu Jeng
  • Publication number: 20170098607
    Abstract: Various structures having a fuse and methods for forming those structures are described. An embodiment is a method. The method comprises attaching a first die to a first side of a component using first electrical connectors. After the attaching, at least one of (i) the first die comprises a first fuse, (ii) the first side of the component comprises a second fuse, (iii) a second side of the component comprises a third fuse, the second side being opposite the first side, or (iv) a combination thereof. The method further comprises after the attaching the first die to the first side of the component, blowing the first fuse, the second fuse, the third fuse, or a combination thereof.
    Type: Application
    Filed: December 14, 2016
    Publication date: April 6, 2017
    Inventors: Chung-Yu Lu, Hsien-Pin Hu, Shin-Puu Jeng, Shang-Yun Hou, Tzuan-Horng Liu, Shih-Wen Huang, Chun Hua Chang
  • Patent number: 9530730
    Abstract: Various structures having a fuse and methods for forming those structures are described. An embodiment is a method. The method comprises attaching a first die to a first side of a component using first electrical connectors. After the attaching, at least one of (i) the first die comprises a first fuse, (ii) the first side of the component comprises a second fuse, (iii) a second side of the component comprises a third fuse, the second side being opposite the first side, or (iv) a combination thereof. The method further comprises after the attaching the first die to the first side of the component, blowing the first fuse, the second fuse, the third fuse, or a combination thereof.
    Type: Grant
    Filed: November 8, 2013
    Date of Patent: December 27, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Yu Lu, Hsien-Pin Hu, Shin-Puu Jeng, Shang-Yun Hou, Tzuan-Horng Liu, Shih-Wen Huang, Chun Hua Chang
  • Publication number: 20160204079
    Abstract: Methods and apparatus for forming a semiconductor device package on an interposer using a micro-bump layer are disclosed. The micro-bump layer may comprise micro-bumps and micro-bump lines, where a micro-bump is used as a vertical connection between a die and the interposer, and a micro-bump line is used as a horizontal connection for signal transmission between different dies above the interposer. The micro-bump lines may be formed at the same time as the formation of the micro-bumps with little or no additional cost.
    Type: Application
    Filed: March 23, 2016
    Publication date: July 14, 2016
    Inventors: Chung-Yu Lu, Hsien-Pin Hu, Hsiao-Tsung Yen, Tzuan-Horng Liu, Shih-Wen Huang, Shang-Yun Hou, Shin-Puu Jeng
  • Patent number: 9305808
    Abstract: Methods and apparatus for forming a semiconductor device package on an interposer using a micro-bump layer are disclosed. The micro-bump layer may comprise micro-bumps and micro-bump lines, where a micro-bump is used as a vertical connection between a die and the interposer, and a micro-bump line is used as a horizontal connection for signal transmission between different dies above the interposer. The micro-bump lines may be formed at the same time as the formation of the micro-bumps with little or no additional cost.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: April 5, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Yu Lu, Hsien-Pin Hu, Hsiao-Tsung Yen, Tzuan-Horng Liu, Shih-Wen Huang, Shang-Yun Hou, Shin-Puu Jeng
  • Publication number: 20160043434
    Abstract: A graft copolymer comprising a backbone polymer and a branched-chain polymer, and represented by formula (I), where A, B, Ra, Rb, Rc, Rd, Re, Rf, G1, G2, G3, G4, Y1, Y2, and k are as defined in the specification. A process for producing the grate copolymer, a process for preparing a gel polymer electrolyte including the graft copolymer, and an intermediate copolymer of the graft copolymer are also disclosed.
    Type: Application
    Filed: August 11, 2014
    Publication date: February 11, 2016
    Inventors: Ping-Lin KUO, Sheng-Shu HOU, Chung-Yu LU, Ching-An WU, Chih-Hao TSAO, Chun-Han HSU
  • Publication number: 20150249019
    Abstract: Methods and apparatus for forming a semiconductor device package on an interposer using a micro-bump layer are disclosed. The micro-bump layer may comprise micro-bumps and micro-bump lines, where a micro-bump is used as a vertical connection between a die and the interposer, and a micro-bump line is used as a horizontal connection for signal transmission between different dies above the interposer. The micro-bump lines may be formed at the same time as the formation of the micro-bumps with little or no additional cost.
    Type: Application
    Filed: May 15, 2015
    Publication date: September 3, 2015
    Inventors: Chung-Yu Lu, Hsien-Pin Hu, Hsiao-Tsung Yen, Tzuan-Horng Liu, Shih-Wen Huang, Shang-Yun Hou, Shin-Puu Jeng
  • Patent number: 9064705
    Abstract: Methods and apparatus for forming a semiconductor device package on an interposer using a micro-bump layer are disclosed. The micro-bump layer may comprise micro-bumps and micro-bump lines, where a micro-bump is used as a vertical connection between a die and the interposer, and a micro-bump line is used as a horizontal connection for signal transmission between different dies above the interposer. The micro-bump lines may be formed at the same time as the formation of the micro-bumps with little or no additional cost.
    Type: Grant
    Filed: December 13, 2012
    Date of Patent: June 23, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Yu Lu, Hsien-Pin Hu, Hsiao-Tsung Yen, Tzuan-Horng Liu, Shih-Wen Huang, Shang-Yun Hou, Shin-Puu Jeng
  • Publication number: 20150130082
    Abstract: Various structures having a fuse and methods for forming those structures are described. An embodiment is a method. The method comprises attaching a first die to a first side of a component using first electrical connectors. After the attaching, at least one of (i) the first die comprises a first fuse, (ii) the first side of the component comprises a second fuse, (iii) a second side of the component comprises a third fuse, the second side being opposite the first side, or (iv) a combination thereof. The method further comprises after the attaching the first die to the first side of the component, blowing the first fuse, the second fuse, the third fuse, or a combination thereof.
    Type: Application
    Filed: November 8, 2013
    Publication date: May 14, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Yu Lu, Hsien-Pin Hu, Shin-Puu Jeng, Shang-Yun Hou, Tzuan-Horng Liu, Shih-Wen Huang, Chun Hua Chang
  • Publication number: 20150102482
    Abstract: Various embodiments of mechanisms for forming through a three-dimensional integrated circuit (3DIC) structure are provided. The 3DIC structure includes an interposer bonded to a die and a substrate. The interposer has a conductive structure with through silicon vias (TSVs) connected to a patterned metal pad and a conductive structure on opposite ends of the TSVs. The pattern metal pad is embedded with dielectric structures to reduce dishing effect and has regions over TSVs that are free of the dielectric structures. The conductive structure has 2 or more TSVs. By using a patterned metal pad and 2 or more TSVs, the reliability and yield of the conductive structure and the 3DIC structure are improved.
    Type: Application
    Filed: October 11, 2013
    Publication date: April 16, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzuan-Horng Liu, Shih-Wen Huang, Chung-Yu Lu, Hsien-Pin Hu, Shang-Yun Hou, Shin-Puu Jeng
  • Publication number: 20150031184
    Abstract: A method of manufacturing a package may include: providing a first device having a first redistribution layer (RDL) and an insulator layer disposed over the first RDL; and forming a first micro-bump line over the insulator layer of the first device. The first micro-bump line may extend laterally over a surface of the insulator layer facing away from the first RDL, and a first inductor of the package comprises the first RDL and the first micro-bump line.
    Type: Application
    Filed: October 14, 2014
    Publication date: January 29, 2015
    Inventors: Hsiao-Tsung Yen, Min-Chie Jeng, Hsien-Pin Hu, Tzuan-Horng Liu, Chin-Wei Kuo, Chung-Yu Lu, Yu-Ling Lin