Patents by Inventor Chung-Yuan TSAI
Chung-Yuan TSAI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230378140Abstract: A semiconductor package including a first semiconductor die, a second semiconductor die, a first insulating encapsulation, a dielectric layer structure, a conductor structure and a second insulating encapsulation is provided. The first semiconductor die includes a first semiconductor substrate and a through substrate via (TSV) extending from a first side to a second side of the semiconductor substrate. The second semiconductor die is disposed on the first side of the semiconductor substrate. The first insulating encapsulation on the second semiconductor die encapsulates the first semiconductor die. A terminal of the TSV is coplanar with a surface of the first insulating encapsulation. The dielectric layer structure covers the first semiconductor die and the first insulating encapsulation. The conductor structure extends through the dielectric layer structure and contacts with the through substrate via.Type: ApplicationFiled: August 1, 2023Publication date: November 23, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hao-Yi Tsai, Cheng-Chieh Hsieh, Tsung-Hsien Chiang, Hui-Chun Chiang, Tzu-Sung Huang, Ming-Hung Tseng, Kris Lipu Chuang, Chung-Ming Weng, Tsung-Yuan Yu, Tzuan-Horng Liu
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Publication number: 20230367062Abstract: Disclosed are semiconductor packages and manufacturing method of the semiconductor packages. In one embodiment, a semiconductor package includes a substrate, a first waveguide, a semiconductor die, and an adhesive layer. The first waveguide is disposed on the substrate. The semiconductor die is disposed on the substrate and includes a second waveguide aligned with the first waveguide. The adhesive layer is disposed between the first waveguide and the second waveguide.Type: ApplicationFiled: July 25, 2023Publication date: November 16, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Ming Weng, Hua-Kuei Lin, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Che-Hsiang Hsu, Chewn-Pu Jou, Cheng-Tse Tang
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Patent number: 11809000Abstract: A photonic integrated circuit includes a substrate, an interconnection layer, and a plurality of silicon waveguides. The interconnection layer is over the substrate. The interconnection layer includes a seal ring structure and an interconnection structure surrounded by the seal ring structure. The seal ring structure has at least one recess from a top view. The recess concaves towards the interconnection structure. The silicon waveguides are embedded in the substrate.Type: GrantFiled: March 19, 2021Date of Patent: November 7, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Yuan Yu, Hung-Yi Kuo, Cheng-Chieh Hsieh, Hao-Yi Tsai, Chung-Ming Weng, Hua-Kuei Lin, Che-Hsiang Hsu
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Patent number: 11768338Abstract: An optical interconnect structure including a base substrate, an optical waveguide, a first reflector, a second reflector, a dielectric layer, a first lens, and a second lens is provided. The optical waveguide is embedded in the base substrate. The optical waveguide includes a first end portion and a second end portion opposite to the first end portion. The first reflector is disposed between the base substrate and the first end portion of the optical waveguide. The second reflector is disposed between the base substrate and the second end portion of the optical waveguide. The dielectric layer covers the base substrate and the optical waveguide. The first lens is disposed on the dielectric layer and located above the first end portion of the optical waveguide. The second lens is disposed on the dielectric layer and located above the second end portion of the optical waveguide.Type: GrantFiled: May 27, 2021Date of Patent: September 26, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Yu-Hsiang Hu, Chewn-Pu Jou, Feng-Wei Kuo
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Patent number: 11754780Abstract: Disclosed are semiconductor packages and manufacturing method of the semiconductor packages. In one embodiment, a semiconductor package includes a substrate, a first waveguide, a semiconductor die, and an adhesive layer. The first waveguide is disposed on the substrate. The semiconductor die is disposed on the substrate and includes a second waveguide aligned with the first waveguide. The adhesive layer is disposed between the first waveguide and the second waveguide.Type: GrantFiled: May 13, 2021Date of Patent: September 12, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Ming Weng, Hua-Kuei Lin, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Che-Hsiang Hsu, Chewn-Pu Jou, Cheng-Tse Tang
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Publication number: 20230280558Abstract: A package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler; an interconnect structure over the photonic layer; an electronic die and a first dielectric layer over the interconnect structure, where the electronic die is connected to the interconnect structure; a first substrate bonded to the electronic die and the first dielectric layer; a socket attached to a top surface of the first substrate; and a fiber holder coupled to the first substrate through the socket, where the fiber holder includes a prism that re-orients an optical path of an optical signal.Type: ApplicationFiled: May 5, 2023Publication date: September 7, 2023Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Che-Hsiang Hsu
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Publication number: 20230258881Abstract: A semiconductor device includes an optical connector element and an optical coupler. The optical connector element includes a base structure, a first polymer via and a cladding layer. The base structure has a first surface and a second surface opposite to the first surface. The first polymer via passes through the base structure from the first surface to the second surface. The cladding layer is surrounding the first polymer via, wherein a refractive index of the cladding layer is different than a refractive index of the first polymer via. The optical coupler is disposed over the optical connector element, wherein the optical coupler receives optical signals from the first polymer via.Type: ApplicationFiled: February 17, 2022Publication date: August 17, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Ming Weng, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Yu-Hao Chen
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Publication number: 20230253300Abstract: A chip package structure includes an interposer structure that contains a package-side redistribution structure, an interposer core assembly, and a die-side redistribution structure. The interposer core assembly includes at least one silicon substrate interposer, and each of the at least one silicon substrate interposer includes a respective silicon substrate, a respective set of through-silicon via (TSV) structures vertically extending through the respective silicon substrate, a respective set of interconnect-level dielectric layers embedding a respective set of metal interconnect structures, and a respective set of metal bonding structures that are electrically connected to the die-side redistribution structure. The chip package structure includes at least two semiconductor dies that are attached to the die-side redistribution structure, and an epoxy molding compound (EMC) multi-die frame that laterally encloses the at least two semiconductor dies.Type: ApplicationFiled: March 28, 2023Publication date: August 10, 2023Inventors: Kuo Lung Pan, Yu-Chia Lai, Teng-Yuan Lo, Mao-Yen Chang, Po-Yuan Teng, Chen-Hua YU, Chung-Shi Liu, Hao-Yi Tsai, Ting-Hao Kuo
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Publication number: 20230245967Abstract: A manufacturing method of a semiconductor package includes the following steps. A supporting layer is formed over a redistribution structure. A first planarization process is performed over the supporting layer. A lower dielectric layer is formed over the supporting layer, wherein the lower dielectric layer includes a concave exposing a device mounting region of the supporting layer. A first sacrificial layer is formed over the supporting layer, wherein the sacrificial layer filling the concave. A second planarization process is performed over the lower dielectric layer and the first sacrificial layer. A transition waveguide provided over the lower dielectric layer. The first sacrificial layer is removed. A semiconductor device is mounted over the device mounting region, wherein the semiconductor device includes a device waveguide is optically coupled to the transition waveguide.Type: ApplicationFiled: March 27, 2023Publication date: August 3, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Hsiu-Jen Lin, Ming-Che Ho, Yu-Hsiang Hu, Chewn-Pu Jou, Cheng-Tse Tang
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Publication number: 20230236372Abstract: Photonic devices and methods of manufacture are provided. In embodiments a fill material and/or a secondary waveguide are utilized in order to protect other internal structures such as grating couplers from the rigors of subsequent processing steps. Through the use of these structures at the appropriate times during the manufacturing process, damage and debris that would otherwise interfere with the manufacturing process of the device or operation of the device can be avoided.Type: ApplicationFiled: March 27, 2023Publication date: July 27, 2023Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Chih-Hsuan Tai, Hua-Kuei Lin, Tsung-Yuan Yu, Min-Hsiang Hsu
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Publication number: 20230235742Abstract: A portable electric fan is provided and includes a shell, a fan module, and a plurality of combined seat groups. The shell has a first surface, a second surface opposite to the first surface, and a surrounding side surface that is connected to the first surface and the second surface. The shell has a hollow portion. The fan module is mounted in the hollow portion. The combined seat groups are mounted on the surrounding side surface, and each of the combined seat groups includes two bases and a bracket detachably mounted to the two bases. Each of the two bases has a first through hole and a second through hole, and an extending length direction of the first through hole and an extending direction of the second through hole are staggered relative to the surrounding side surface.Type: ApplicationFiled: April 14, 2022Publication date: July 27, 2023Inventors: CHUNG-YU LIN, CHIA-WEI CHANG, KAI-JEN TSAI, MIN-YUAN HSIAO
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Publication number: 20230230969Abstract: The disclosure provides an electronic device, including: a circuit substrate, an inorganic light emitting unit, and an opaque layer. The circuit substrate includes an optical sensor. The inorganic light emitting unit is disposed on the circuit substrate and is configured to emit a light. The opaque layer is disposed on the circuit substrate, including a first opening through which a portion of the light is transmitted to the optical sensor.Type: ApplicationFiled: December 16, 2022Publication date: July 20, 2023Applicant: Innolux CorporationInventors: Chiu-Lien Yang, Jia-Yuan Chen, Tsung-Han Tsai, Kuan-Feng Lee, Chung-Wen Yen
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Patent number: 11705413Abstract: A semiconductor package including a base comprising an upper surface and a lower surface that is opposite to the upper surface; a radio-frequency (RF) module embedded near the upper surface of the base; an integrated circuit (IC) die mounted on the lower surface of the base in a flip-chip manner so that a backside of the IC die is available for heat dissipation; a plurality of conductive structures disposed on the lower surface of the base and arranged around the IC die; and a metal thermal interface layer comprising a backside metal layer that is in contact with the backside of the IC die, and a solder paste conformally printed on the backside metal layer.Type: GrantFiled: December 14, 2021Date of Patent: July 18, 2023Assignee: MEDIATEK INC.Inventors: Chia-Hao Hsu, Tai-Yu Chen, Shiann-Tsong Tsai, Hsing-Chih Liu, Yao-Pang Hsu, Chi-Yuan Chen, Chung-Fa Lee
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Publication number: 20230201423Abstract: The invention relates to a cell sheet construct for neurovascular reconstruction. The cell sheet construct has a vascular endothelial cell layer and a neural stem cell layer, and the two layers are physically in direct contact with each other, where the vascular endothelial cell layer forms branching vasculatures, and the neural stem cell layer differentiates into neurons. The invention also relates to a method for manufacturing the cell sheet construct, having the following steps: culturing vascular endothelial cells on a substrate to form a vascular endothelial cell layer, seeding neural stem cells on the vascular endothelial cell layer to make the neural stem cells be physically in direct contact with the vascular endothelial cell layer, and culturing the neural stem cells and the vascular endothelial cell layer to differentiate into neurons and branching vasculatures to form a cell sheet construct.Type: ApplicationFiled: March 2, 2023Publication date: June 29, 2023Inventors: Chung-Hsing CHOU, Dueng-Yuan Hueng, Tsung-Neng TSAI
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Patent number: 11686908Abstract: A package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler; an interconnect structure over the photonic layer; an electronic die and a first dielectric layer over the interconnect structure, where the electronic die is connected to the interconnect structure; a first substrate bonded to the electronic die and the first dielectric layer; a socket attached to a top surface of the first substrate; and a fiber holder coupled to the first substrate through the socket, where the fiber holder includes a prism that re-orients an optical path of an optical signal.Type: GrantFiled: January 3, 2022Date of Patent: June 27, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Che-Hsiang Hsu
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Patent number: 11661946Abstract: A ceiling fan and a surrounding device thereof are provided. The ceiling fan includes a main body, a bracket set connected to the main body, and a surrounding device connected to the bracket set. The main body includes a main shaft, a motor, and a plurality of ceiling fan blades. The bracket set includes a plurality of brackets, and each of the brackets has one end connected to the main shaft. The surrounding device is connected to another end of each of the brackets that is relatively far away from the main shaft, and the surrounding device is roundly arranged around and spaced apart from an end of each of the ceiling fan blades that is relatively far away from the motor. The surrounding device includes at least one functional component that is configured to disinfect or sterilize air or to provide lighting.Type: GrantFiled: January 6, 2022Date of Patent: May 30, 2023Assignee: HOTECK INC.Inventors: Chia-Wei Chang, Kai-Jen Tsai, Meng-Yuan Lee, Chung-Yu Lin, Min-Yuan Hsiao
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Patent number: 11652014Abstract: An electronic package and method for manufacturing the same are provided. The electronic package includes a first conductive structure, a second conductive structure, an electronic component, an underfill and a dam structure. The second conductive structure is disposed on the first conductive structure, wherein the second conductive structure defines a cavity over the first conductive structure. The electronic component is disposed on the first conductive structure and at least partially disposed in the cavity. The underfill is disposed between the first conductive structure and the electronic component. The dam structure is disposed on the first conductive structure and configured to confine the underfill.Type: GrantFiled: September 30, 2020Date of Patent: May 16, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventor: Chung-Yuan Tsai
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Publication number: 20220102233Abstract: An electronic package and method for manufacturing the same are provided. The electronic package includes a first conductive structure, a second conductive structure, an electronic component, an underfill and a dam structure. The second conductive structure is disposed on the first conductive structure, wherein the second conductive structure defines a cavity over the first conductive structure. The electronic component is disposed on the first conductive structure and at least partially disposed in the cavity. The underfill is disposed between the first conductive structure and the electronic component. The dam structure is disposed on the first conductive structure and configured to confine the underfill.Type: ApplicationFiled: September 30, 2020Publication date: March 31, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventor: Chung-Yuan TSAI
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Patent number: D1004070Type: GrantFiled: January 27, 2022Date of Patent: November 7, 2023Assignee: HOTECK INC.Inventors: Chung-Yu Lin, Chia-Wei Chang, Kai-Jen Tsai, Min-Yuan Hsiao