Abstract: The present invention relates to a method of manufacturing a non-volatile memory cell. The method comprises forming an ONO stack and a mask formed on the ONO stack, providing a first etching process to form a first spacer surrounding the mask, removing portions of the first spacer and the ONO stack that are not covered by the first spacer and the ONO stack, forming an electrical connection layer between the masks, forming a second spacer surrounding the mask, removing the second spacer to form a gate and removing the mask and the ONO stack which is under the mask.

Abstract: The present invention relates to a method of manufacturing a non-volatile memory cell. The method comprises forming an ONO stack structure and a mask formed on the ONO stack structure, providing a first etching process to form a first spacer surrounding the mask, removing the first spacer and the ONO stack structure without the first spacer and the ONO stack structure protection, forming an electrical connection layer between the masks, forming a second spacer surrounding the mask, removing the second spacer to form a gate and removing the mask and the ONO stack structure which is under the mask.

Abstract: A method for programming a single-bit storage nonvolatile memory cell includes the steps of: providing a single-bit storage nonvolatile memory cell having a channel region between a left bit line and a right bit line, a composite dielectric layer for storing digital data, and a word line overlying the composite dielectric layer, performing a left side electron injection on the single-bit storage nonvolatile memory cell by applying a relatively high word line voltage to the word line, applying a relatively high left bit line voltage to the left bit line, and applying a relatively low right bit line voltage to the right bit line; and performing a right side electron injection by applying the relatively high word line voltage to the word line, applying a relatively low left bit line voltage to the left bit line, and applying a relatively high right bit line voltage to the right bit line.

Abstract: A method for programming a single-bit storage nonvolatile memory cell includes the steps of: providing a single-bit storage nonvolatile memory cell having a channel region between a left bit line and a right bit line, a composite dielectric layer for storing digital data, and a word line overlying the composite dielectric layer; performing a left side electron injection on the single-bit storage nonvolatile memory cell by applying a relatively high word line voltage (VWL, HIGH) to the word line, applying a relatively high left bit line voltage (VLBL, HIGH) to the left bit line, and applying a relatively low right bit line voltage (VRBL, LOW) to the right bit line; and performing a right side electron injection on the single-bit storage nonvolatile memory cell by applying the relatively high word line voltage (VWL, HIGH) to the word line, applying a relatively low left bit line voltage (VLBL, LOW) to the left bit line, and applying a relatively high right bit line voltage (VRBL, HIGH) to the right bit line.

Abstract: A method for programming a single-poly EPROM cell at relatively low operation voltages (±Vcc) is disclosed. According to this invention, the single-poly EPROM cell includes a P-channel floating-gate transistor formed on an N well of a P type substrate, and an N-channel coupling device. The P-channel floating-gate transistor has a P+ doped drain, P+ doped source, a P channel defined between the P+ doped drain and P+ doped source, a tunnel oxide layer on the P channel, and a floating doped poly gate disposed on the tunnel oxide layer. The N-channel coupling device includes a floating poly electrode, which is electrically connected to the floating doped poly gate of the P-channel floating-gate transistor, and is capacitively coupled to a control region doped in the P type substrate.

Abstract: An electrically programmable non-volatile memory cell is provided. A semiconductor substrate is prepared. A pair of spaced apart source/drain (S/D) regions is defined on the semiconductor substrate. The spaced apart S/D regions define a channel region in between. A first dielectric layer such as silicon dioxide is disposed on the S/D regions. An assistant gate is stacked on the first dielectric layer. The assistant gate has a top surface and sidewalls. A second dielectric layer comprising a charge-trapping layer is uniformly disposed on the top surface and sidewalls of the assistant gate and is also disposed on the channel region. The second dielectric layer provides a recessed trough between the S/D regions. A conductive gate material fills the recessed trough for controlling said channel region.