Patents by Inventor Chung-Hwan Shin
Chung-Hwan Shin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11923426Abstract: A semiconductor device capable of improving a device performance and a reliability is provided. The semiconductor device comprising a gate structure including a gate electrode on a substrate, a source/drain pattern on a side face of the gate electrode, on the substrate and, a source/drain contact connected to the source/drain pattern, on the source/drain pattern, a gate contact connected to the gate electrode, on the gate electrode, and a wiring structure connected to the source/drain contact and the gate contact, on the source/drain contact and the gate contact, wherein the wiring structure includes a first via plug, a second via plug, and a wiring line connected to the first via plug and the second via plug, the first via plug has a single conductive film structure, and the second via plug includes a lower via filling film, and an upper via filling film on the lower via filling film.Type: GrantFiled: July 6, 2021Date of Patent: March 5, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Ji Won Kang, Tae-Yeol Kim, Jeong Ik Kim, Rak Hwan Kim, Jun Ki Park, Chung Hwan Shin
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Publication number: 20240014250Abstract: A semiconductor device is provided including a resistor structure, the semiconductor device including a substrate having an upper surface perpendicular to a first direction; a resistor structure including a first insulating layer on the substrate, a resistor layer on the first insulating layer, and a second insulating layer on the resistor layer; and a resistor contact penetrating the second insulating layer and the resistor layer. The tilt angle of a side wall of the resistor contact with respect to the first direction varies according to a height from the substrate. The semiconductor device has a low contact resistance and a narrow variation of contact resistance.Type: ApplicationFiled: September 21, 2023Publication date: January 11, 2024Inventors: Tae-yeol KIM, Hyon-wook RA, Seo-bum LEE, Jun-soo KIM, Chung-hwan SHIN
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Patent number: 11804516Abstract: A semiconductor device is provided including a resistor structure, the semiconductor device including a substrate having an upper surface perpendicular to a first direction; a resistor structure including a first insulating layer on the substrate, a resistor layer on the first insulating layer, and a second insulating layer on the resistor layer; and a resistor contact penetrating the second insulating layer and the resistor layer. The tilt angle of a side wall of the resistor contact with respect to the first direction varies according to a height from the substrate. The semiconductor device has a low contact resistance and a narrow variation of contact resistance.Type: GrantFiled: December 10, 2020Date of Patent: October 31, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Tae-yeol Kim, Hyon-wook Ra, Seo-bum Lee, Jun-soo Kim, Chung-hwan Shin
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Publication number: 20220319916Abstract: A semiconductor device includes a first interlayer insulating film; a conductive connection structure provided in the first interlayer insulating film; a second interlayer insulating film provided on the first interlayer insulating film; a wiring structure provided in the second interlayer insulating film and connected to the conductive connection structure; and an insertion liner interposed between an upper surface of the conductive connection structure and the wiring structure, the insertion liner including carbon.Type: ApplicationFiled: June 13, 2022Publication date: October 6, 2022Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Won Keun CHUNG, Joon Gon LEE, Rak Hwan KIM, Chung Hwan SHIN, Do Sun LEE, Nam Gyu CHO
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Patent number: 11367651Abstract: A semiconductor device includes a first interlayer insulating film; a conductive connection structure provided in the first interlayer insulating film; a second interlayer insulating film provided on the first interlayer insulating film; a wiring structure provided in the second interlayer insulating film and connected to the conductive connection structure; and an insertion liner interposed between an upper surface of the conductive connection structure and the wiring structure, the insertion liner including carbon.Type: GrantFiled: June 16, 2020Date of Patent: June 21, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Won Keun Chung, Joon Gon Lee, Rak Hwan Kim, Chung Hwan Shin, Do Sun Lee, Nam Gyu Cho
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Publication number: 20220130970Abstract: A semiconductor device capable of improving a device performance and a reliability is provided. The semiconductor device comprising a gate structure including a gate electrode on a substrate, a source/drain pattern on a side face of the gate electrode, on the substrate and, a source/drain contact connected to the source/drain pattern, on the source/drain pattern, a gate contact connected to the gate electrode, on the gate electrode, and a wiring structure connected to the source/drain contact and the gate contact, on the source/drain contact and the gate contact, wherein the wiring structure includes a first via plug, a second via plug, and a wiring line connected to the first via plug and the second via plug, the first via plug has a single conductive film structure, and the second via plug includes a lower via filling film, and an upper via filling film on the lower via filling film.Type: ApplicationFiled: July 6, 2021Publication date: April 28, 2022Inventors: Ji Won KANG, Tae-Yeol KIM, Jeong Ik KIM, Rak Hwan KIM, Jun Ki PARK, Chung Hwan SHIN
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Publication number: 20210098563Abstract: A semiconductor device is provided including a resistor structure, the semiconductor device including a substrate having an upper surface perpendicular to a first direction; a resistor structure including a first insulating layer on the substrate, a resistor layer on the first insulating layer, and a second insulating layer on the resistor layer; and a resistor contact penetrating the second insulating layer and the resistor layer. The tilt angle of a side wall of the resistor contact with respect to the first direction varies according to a height from the substrate. The semiconductor device has a low contact resistance and a narrow variation of contact resistance.Type: ApplicationFiled: December 10, 2020Publication date: April 1, 2021Inventors: Tae-yeol KIM, Hyon-wook RA, Seo-bum LEE, Jun-soo KIM, Chung-hwan SHIN
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Publication number: 20210020500Abstract: A semiconductor device includes a first interlayer insulating film; a conductive connection structure provided in the first interlayer insulating film; a second interlayer insulating film provided on the first interlayer insulating film; a wiring structure provided in the second interlayer insulating film and connected to the conductive connection structure; and an insertion liner interposed between an upper surface of the conductive connection structure and the wiring structure, the insertion liner including carbon.Type: ApplicationFiled: June 16, 2020Publication date: January 21, 2021Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Won Keun Chung, Joon Gon Lee, Rak Hwan Kim, Chung Hwan Shin, Do Sun Lee, Nam Gyu Cho
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Patent number: 10886361Abstract: A semiconductor device is provided including a resistor structure, the semiconductor device including a substrate having an upper surface perpendicular to a first direction; a resistor structure including a first insulating layer on the substrate, a resistor layer on the first insulating layer, and a second insulating layer on the resistor layer; and a resistor contact penetrating the second insulating layer and the resistor layer. The tilt angle of a side wall of the resistor contact with respect to the first direction varies according to a height from the substrate. The semiconductor device has a low contact resistance and a narrow variation of contact resistance.Type: GrantFiled: January 5, 2018Date of Patent: January 5, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Tae-yeol Kim, Hyon-wook Ra, Seo-bum Lee, Jun-soo Kim, Chung-hwan Shin
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Patent number: 10847464Abstract: A semiconductor device and a method of forming the same, the semiconductor device including an insulating structure having an opening; a conductive pattern disposed in the opening; a barrier structure covering a bottom surface of the conductive pattern, the barrier structure extending between the conductive pattern and side walls of the opening; and a nucleation structure disposed between the conductive pattern and the barrier structure. The nucleation structure includes a first nucleation layer that contacts the barrier structure, and a second nucleation layer that contacts the conductive pattern, and a top end portion of the second nucleation layer is higher than a top end portion of the first nucleation layer.Type: GrantFiled: January 9, 2020Date of Patent: November 24, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Tae Yeol Kim, Ji Won Kang, Chung Hwan Shin, Jin Il Lee, Sang Jin Hyun
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Patent number: 10840374Abstract: A method of forming a semiconductor device can be provided by forming an opening that exposes a surface of an elevated source/drain region. The size of the opening can be reduced and a pre-amorphization implant (PAI) can be performed into the elevated source/drain region, through the opening, to form an amorphized portion of the elevated source/drain region. A metal-silicide can be formed from a metal and the amorphized portion.Type: GrantFiled: July 3, 2018Date of Patent: November 17, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chung-Hwan Shin, Sang-Bom Kang, Dae-Yong Kim, Jeong-Ik Kim, Chul-Sung Kim, Je-Hyung Ryu, Sang-Woo Lee, Hyo-Seok Choi
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Publication number: 20200152577Abstract: A semiconductor device and a method of forming the same, the semiconductor device including an insulating structure having an opening; a conductive pattern disposed in the opening; a barrier structure covering a bottom surface of the conductive pattern, the barrier structure extending between the conductive pattern and side walls of the opening; and a nucleation structure disposed between the conductive pattern and the barrier structure. The nucleation structure includes a first nucleation layer that contacts the barrier structure, and a second nucleation layer that contacts the conductive pattern, and a top end portion of the second nucleation layer is higher than a top end portion of the first nucleation layer.Type: ApplicationFiled: January 9, 2020Publication date: May 14, 2020Inventors: TAE YEOL KIM, JI WON KANG, CHUNG HWAN SHIN, JIN IL LEE, SANG JIN HYUN
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Patent number: 10580736Abstract: A semiconductor device and a method of forming the same, the semiconductor device including an insulating structure having an opening; a conductive pattern disposed in the opening; a barrier structure covering a bottom surface of the conductive pattern, the barrier structure extending between the conductive pattern and side walls of the opening; and a nucleation structure disposed between the conductive pattern and the barrier structure. The nucleation structure includes a first nucleation layer that contacts the barrier structure, and a second nucleation layer that contacts the conductive pattern, and a top end portion of the second nucleation layer is higher than a top end portion of the first nucleation layer.Type: GrantFiled: June 14, 2019Date of Patent: March 3, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Tae Yeol Kim, Ji Won Kang, Chung Hwan Shin, Jin Il Lee, Sang Jin Hyun
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Publication number: 20190295958Abstract: A semiconductor device and a method of forming the same, the semiconductor device including an insulating structure having an opening; a conductive pattern disposed in the opening; a barrier structure covering a bottom surface of the conductive pattern, the barrier structure extending between the conductive pattern and side walls of the opening; and a nucleation structure disposed between the conductive pattern and the barrier structure. The nucleation structure includes a first nucleation layer that contacts the barrier structure, and a second nucleation layer that contacts the conductive pattern, and a top end portion of the second nucleation layer is higher than a top end portion of the first nucleation layer.Type: ApplicationFiled: June 14, 2019Publication date: September 26, 2019Inventors: TAE YEOL KIM, JI WON KANG, CHUNG HWAN SHIN, JIN IL LEE, SANG JIN HYUN
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Patent number: 10366955Abstract: A semiconductor device and a method of forming the same, the semiconductor device including an insulating structure having an opening; a conductive pattern disposed in the opening; a barrier structure covering a bottom surface of the conductive pattern, the barrier structure extending between the conductive pattern and side walls of the opening; and a nucleation structure disposed between the conductive pattern and the barrier structure. The nucleation structure includes a first nucleation layer that contacts the barrier structure, and a second nucleation layer that contacts the conductive pattern, and a top end portion of the second nucleation layer is higher than a top end portion of the first nucleation layer.Type: GrantFiled: November 8, 2017Date of Patent: July 30, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Tae Yeol Kim, Ji Won Kang, Chung Hwan Shin, Jin Il Lee, Sang Jin Hyun
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Publication number: 20180374915Abstract: A semiconductor device is provided including a resistor structure, the semiconductor device including a substrate having an upper surface perpendicular to a first direction; a resistor structure including a first insulating layer on the substrate, a resistor layer on the first insulating layer, and a second insulating layer on the resistor layer; and a resistor contact penetrating the second insulating layer and the resistor layer. The tilt angle of a side wall of the resistor contact with respect to the first direction varies according to a height from the substrate. The semiconductor device has a low contact resistance and a narrow variation of contact resistance.Type: ApplicationFiled: January 5, 2018Publication date: December 27, 2018Inventors: Tae-yeol KIM, Hyon-wook RA, Seo-bum LEE, Jun-soo KIM, Chung-hwan SHIN
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Publication number: 20180331218Abstract: A method of forming a semiconductor device can be provided by forming an opening that exposes a surface of an elevated source/drain region. The size of the opening can be reduced and a pre-amorphization implant (PAI) can be performed into the elevated source/drain region, through the opening, to form an amorphized portion of the elevated source/drain region. A metal-silicide can be formed from a metal and the amorphized portion.Type: ApplicationFiled: July 3, 2018Publication date: November 15, 2018Inventors: Chung-Hwan Shin, Sang-Bom Kang, Dae-Yong Kim, Jeong-lk Kim, Chul-Sung Kim, Je-Hyung Ryu, Sang-Woo Lee, Hyo-Seok Choi
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Patent number: 10043902Abstract: A method of forming a semiconductor device can be provided by forming an opening that exposes a surface of an elevated source/drain region. The size of the opening can be reduced and a pre-amorphization implant (PAI) can be performed into the elevated source/drain region, through the opening, to form an amorphized portion of the elevated source/drain region. A metal-silicide can be formed from a metal and the amorphized portion.Type: GrantFiled: December 9, 2015Date of Patent: August 7, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Chung-Hwan Shin, Sang-Bom Kang, Dae-Yong Kim, Jeong-Ik Kim, Chul-Sung Kim, Je-Hyung Ryu, Sang-Woo Lee, Hyo-Seok Choi
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Publication number: 20180211922Abstract: A semiconductor device and a method of forming the same, the semiconductor device including an insulating structure having an opening; a conductive pattern disposed in the opening; a barrier structure covering a bottom surface of the conductive pattern, the barrier structure extending between the conductive pattern and side walls of the opening; and a nucleation structure disposed between the conductive pattern and the barrier structure. The nucleation structure includes a first nucleation layer that contacts the barrier structure, and a second nucleation layer that contacts the conductive pattern, and a top end portion of the second nucleation layer is higher than a top end portion of the first nucleation layer.Type: ApplicationFiled: November 8, 2017Publication date: July 26, 2018Inventors: TAE YEOL KIM, JI WON KANG, CHUNG HWAN SHIN, JIN IL LEE, SANG JIN HYUN
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Patent number: 9786764Abstract: A semiconductor device includes an active fin formed to extend in a first direction, a gate formed on the active fin and extending in a second direction crossing the first direction, a source/drain formed on upper portions of the active fin and disposed at one side of the gate, an interlayer insulation layer covering the gate and the source/drain, a source/drain contact passing through the interlayer insulation layer to be connected to the source/drain and including a first contact region and a second contact region positioned between the source/drain and the first contact region, and a spacer layer formed between the first contact region and the interlayer insulation layer. A width of the second contact region in the first direction is greater than the sum of a width of the first contact region in the first direction and a width of the spacer layer in the first direction.Type: GrantFiled: October 22, 2015Date of Patent: October 10, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chan-Jin Park, Chung-Hwan Shin, Sung-Woo Kang, Young-Mook Oh, Sun-Jung Lee, Jeong-Nam Han