Abstract: A three-dimensional flash memory device is described that may include a substrate, a plurality of cell gate patterns and a plurality of mold insulating layers alternately stacked on the substrate, and a vertical channel structure in contact with side surfaces of the plurality of cell gate patterns and side surfaces of the plurality of mold insulating layers. Each of the plurality of cell gate patterns may include a cell gate electrode and a blocking barrier pattern adjacently disposed on one side surface of the cell gate electrode. An inner side surface of the blocking barrier pattern may include an upper inner side surface, a middle inner side surface, and a lower inner side surface. The middle inner side surface of the blocking barrier pattern may face the one side surface of the cell gate electrode.

Abstract: A three-dimensional flash memory device is described that may include a substrate, a plurality of cell gate patterns and a plurality of mold insulating layers alternately stacked on the substrate, and a vertical channel structure in contact with side surfaces of the plurality of cell gate patterns and side surfaces of the plurality of mold insulating layers. Each of the plurality of cell gate patterns may include a cell gate electrode and a blocking barrier pattern adjacently disposed on one side surface of the cell gate electrode. An inner side surface of the blocking barrier pattern may include an upper inner side surface, a middle inner side surface, and a lower inner side surface. The middle inner side surface of the blocking barrier pattern may face the one side surface of the cell gate electrode.