Abstract: A method for fabricating a semiconductor device includes providing a polishing pad which includes a first region and a second region separated from each other by a fence, loading a wafer onto the first region, providing a slurry solution onto the first region, providing an ultrapure water onto the second region, turning the polishing pad to polish a surface of the wafer, and unloading the wafer from the polishing pad after polishing on the surface of the wafer is completed, wherein the fence includes a first fence extending from a center of the polishing pad toward an edge of the polishing pad in a first horizontal direction, and a second fence extending from the center of the polishing pad toward the edge of the polishing pad in a second horizontal direction different from the first horizontal direction.

Abstract: A semiconductor device includes a stacked structure on a substrate. The stacked structure includes stepped regions and a central region between the stepped regions, an upper insulation layer on the stacked structure, and a capping insulation layer on the stepped regions of the stacked structure. The capping insulation layer includes a first upper end portion and a second upper end portion that are adjacent to the upper insulation layer. The upper insulation layer is between the first upper end portion and the second upper end portion. The first upper end portion and the second upper end portion extends a first height relative to the substrate that is different from a second height relative to the substrate of the second upper end portion.

Abstract: A semiconductor device includes a stacked structure on a substrate. The stacked structure includes stepped regions and a central region between the stepped regions, an upper insulation layer on the stacked structure, and a capping insulation layer on the stepped regions of the stacked structure. The capping insulation layer includes a first upper end portion and a second upper end portion that are adjacent to the upper insulation layer. The upper insulation layer is between the first upper end portion and the second upper end portion. The first upper end portion and the second upper end portion extends a first height relative to the substrate that is different from a second height relative to the substrate of the second upper end portion.

Abstract: A semiconductor device includes lower gate electrodes placed on a substrate and spaced apart from one another; upper gate electrodes placed over the lower gate electrodes and spaced apart from one another; an R-type pad extending from one end of at least one electrode among the lower gate electrodes or the upper gate electrodes and having a greater thickness than the lower gate electrode or upper gate electrode connected to the R-type pad; and a P-type pad extending from one end of at least one electrode to which the R-type pad is not connected among the lower gate electrodes or the upper gate electrodes and having a different thickness than the R-type pad, wherein the P-type pad includes a first pad connected to an uppermost lower gate electrode among the lower gate electrodes.

Abstract: A semiconductor device includes a stacked structure on a substrate. The stacked structure includes stepped regions and a central region between the stepped regions, an upper insulation layer on the stacked structure, and a capping insulation layer on the stepped regions of the stacked structure. The capping insulation layer includes a first upper end portion and a second upper end portion that are adjacent to the upper insulation layer. The upper insulation layer is between the first upper end portion and the second upper end portion. The first upper end portion and the second upper end portion extends a first height relative to the substrate that is different from a second height relative to the substrate of the second upper end portion.

Abstract: A semiconductor device includes lower gate electrodes placed on a substrate and spaced apart from one another; upper gate electrodes placed over the lower gate electrodes and spaced apart from one another; an R-type pad extending from one end of at least one electrode among the lower gate electrodes or the upper gate electrodes and having a greater thickness than the lower gate electrode or upper gate electrode connected to the R-type pad; and a P-type pad extending from one end of at least one electrode to which the R-type pad is not connected among the lower gate electrodes or the upper gate electrodes and having a different thickness than the R-type pad, wherein the P-type pad includes a first pad connected to an uppermost lower gate electrode among the lower gate electrodes.

Abstract: A semiconductor device includes a stacked structure on a substrate. The stacked structure includes stepped regions and a central region between the stepped regions, an upper insulation layer on the stacked structure, and a capping insulation layer on the stepped regions of the stacked structure. The capping insulation layer includes a first upper end portion and a second upper end portion that are adjacent to the upper insulation layer. The upper insulation layer is between the first upper end portion and the second upper end portion. The first upper end portion and the second upper end portion extends a first height relative to the substrate that is different from a second height relative to the substrate of the second upper end portion.

Abstract: A semiconductor device includes lower gate electrodes placed on a substrate and spaced apart from one another; upper gate electrodes placed over the lower gate electrodes and spaced apart from one another; an R-type pad extending from one end of at least one electrode among the lower gate electrodes or the upper gate electrodes and having a greater thickness than the lower gate electrode or upper gate electrode connected to the R-type pad; and a P-type pad extending from one end of at least one electrode to which the R-type pad is not connected among the lower gate electrodes or the upper gate electrodes and having a different thickness than the R-type pad, wherein the P-type pad includes a first pad connected to an uppermost lower gate electrode among the lower gate electrodes.

Abstract: A semiconductor device includes lower gate electrodes placed on a substrate and spaced apart from one another; upper gate electrodes placed over the lower gate electrodes and spaced apart from one another; an R-type pad extending from one end of at least one electrode among the lower gate electrodes or the upper gate electrodes and having a greater thickness than the lower gate electrode or upper gate electrode connected to the R-type pad; and a P-type pad extending from one end of at least one electrode to which the R-type pad is not connected among the lower gate electrodes or the upper gate electrodes and having a different thickness than the R-type pad, wherein the P-type pad includes a first pad connected to an uppermost lower gate electrode among the lower gate electrodes.

Abstract: In a semiconductor device having an insulating layer structure and method of manufacturing the same, a substrate including a first region and a second region may be provided. A first pattern structure may be formed on the first region of the substrate. A second pattern structure may be formed on the second region of the substrate, and have a height that is greater than the height of the first pattern structure. An insulating layer structure is formed on the first and second pattern structures and includes a protrusion near an area at which the first and second regions meet each other. An upper surface of the insulating interlayer structure is higher than a top surface of the second pattern structure. The protrusion may have at least one side surface having a staircase shape. A planarized insulating interlayer may be formed without substantial damage to the infrastructure by using the insulating layer structure in accordance with example embodiments.

Abstract: In a semiconductor device having an insulating layer structure and method of manufacturing the same, a substrate including a first region and a second region may be provided. A first pattern structure may be formed on the first region of the substrate. A second pattern structure may be formed on the second region of the substrate, and have a height that is greater than the height of the first pattern structure. An insulating layer structure is formed on the first and second pattern structures and includes a protrusion near an area at which the first and second regions meet each other. An upper surface of the insulating interlayer structure is higher than a top surface of the second pattern structure. The protrusion may have at least one side surface having a staircase shape. A planarized insulating interlayer may be formed without substantial damage to the infrastructure by using the insulating layer structure in accordance with example embodiments.

Abstract: In an embodiment, a chemical mechanical polishing method for a substrate having a first layer and a stepped portion. A surface of the first layer is positioned above an upper face of the stepped portion. A polishing process for selectively removing the stepped portion is performed on the first layer by using a first slurry composition that has a self-stopping characteristic so that the first layer is changed into a second layer having a substantially flat surface. A second polishing process is performed using a second slurry composition that does not have the self-stopping characteristic, until the upper face of the stepped portion is exposed.

Abstract: A chemical-mechanical polishing (CMP) method of polishing a phase-change material and a method of fabricating a phase-change memory, the CMP method including forming the phase-change material on an activation surface of a semiconductor wafer, and performing a CMP process on the phase-change material using a polishing pad, wherein the performing the CMP process includes reducing a change in the composition of the phase-change material by adjusting, within a predetermined range, a temperature of a region where the semiconductor wafer and the polishing pad contact each other.

Abstract: A phase changeable memory device is manufactured by forming at least one insulating layer on a substrate. A preliminary first electrode is formed on the insulating layer. The preliminary first electrode is partially etched to form a first electrode electrically connected to the substrate. After the preliminary first electrode is formed, both sidewalls of the preliminary first electrode are partially etched isotropically to form a first electrode having a uniform width and height. A phase changeable material layer pattern and a second electrode are subsequently formed on the first electrode. Related devices also are described.

Abstract: A chemical-mechanical polishing (CMP) method of polishing a phase-change material and a method of fabricating a phase-change memory, the CMP method including forming the phase-change material on an activation surface of a semiconductor wafer, and performing a CMP process on the phase-change material using a polishing pad, wherein the performing the CMP process includes reducing a change in the composition of the phase-change material by adjusting, within a predetermined range, a temperature of a region where the semiconductor wafer and the polishing pad contact each other.

Abstract: In an embodiment, a chemical mechanical polishing method for a substrate having a first layer and a stepped portion. A surface of the first layer is positioned above an upper face of the stepped portion. A polishing process for selectively removing the stepped portion is performed on the first layer by using a first slurry composition that has a self-stopping characteristic so that the first layer is changed into a second layer having a substantially flat surface. A second polishing process is performed using a second slurry composition that does not have the self-stopping characteristic, until the upper face of the stepped portion is exposed.

Abstract: In an embodiment, a chemical mechanical polishing method for a substrate having a first layer and a stepped portion. A surface of the first layer is positioned above an upper face of the stepped portion. A polishing process for selectively removing the stepped portion is performed on the first layer by using a first slurry composition that has a self-stopping characteristic so that the first layer is changed into a second layer having a substantially flat surface. A second polishing process is performed using a second slurry composition that does not have the self-stopping characteristic, until the upper face of the stepped portion is exposed.

Abstract: Provided is a semiconductor device including a vertically oriented capacitor extending above the substrate surface and a method of manufacturing such devices in which cell, peripheral and boundary areas between the cell and peripheral areas are defined on a semiconductor substrate. Capacitors are formed in the cell area, a mold pattern is provided in the peripheral areas and an elongated dummy pattern is provided in the boundary areas. The dummy pattern includes a boundary opening in which a thin layer is formed on the elongated inner sidewalls and on the exposed portion of the substrate during formation of the lower electrode. A mold pattern and lower electrode structures having substantially the same height are then formed area so that subsequent insulation interlayer(s) exhibit a generally planar surface, i.e., have no significant step difference between the cell areas and the peripheral areas.

Abstract: Example embodiments of the present invention relate to an electrode structure, a method of manufacturing the electrode structure, a phase-change memory device having the electrode structure and a method of manufacturing the phase-change memory device. The electrode structure may include a pad, a first insulation layer pattern, a second insulation layer pattern and/or an electrode. The first insulation layer pattern may be formed on the pad. The first insulation layer pattern may have a first opening that partially exposes the pad. The second insulation layer pattern may be formed on the first insulation layer pattern. The second insulation layer pattern may have a second opening connected to the first opening. The electrode may be formed on the pad and filling the first and the second openings.

Abstract: In a method of manufacturing a semiconductor device, a preliminary insulating layer is formed on a substrate. A photoresist pattern is formed on the preliminary insulating layer. A central portion of the preliminary insulating layer is partially etched using the photoresist pattern as an etch mask to form a preliminary insulating layer pattern including a central portion and a peripheral portion on the substrate. The peripheral portion of the photoresist pattern is higher than that of the central portion of the preliminary insulating layer pattern. The preliminary insulating layer pattern is polished to form a planarized insulating layer on the substrate.