Abstract: A variable resistance memory device includes a first conductive line extending on a substrate in a first horizontal direction; a second conductive line extending on the first conductive line in a second horizontal direction perpendicular to the first horizontal direction; and a memory cell at an intersection between the first conductive line and the second conductive line, the memory cell including a selection element and a variable resistor, wherein the variable resistor includes a first variable resistance layer having a senary component represented by CaGebSbcTedAeXf, in which A and X are each a group 13 element different from each other, and 1?a?18, 13?b?26, 15?c?30, 35?d?55, 0.1?e?8, 0.1?f?8, and a+b+c+d+e+f=100.

Abstract: A chalcogen compound layer exhibiting ovonic threshold switching characteristics, a switching device, a semiconductor device, and/or a semiconductor apparatus including the same are provided. The switching device and/or the semiconductor device may include two or more chalcogen compound layers having different energy band gaps. Alternatively, the switching device and/or semiconductor device may include a chalcogen compound layer having a concentration gradient of an element of boron (B), aluminum (Al), scandium (Sc), manganese (Mn), strontium (Sr), and/or indium (In) in a thickness direction thereof. The switching device and/or a semiconductor device may exhibit stable switching characteristics while having a low off-current value (leakage current value).

Abstract: A chalcogen compound layer exhibiting ovonic threshold switching characteristics, a switching device, a semiconductor device, and/or a semiconductor apparatus including the same are provided. The switching device and/or the semiconductor device may include two or more chalcogen compound layers having different energy band gaps. Alternatively, the switching device and/or semiconductor device may include a chalcogen compound layer having a concentration gradient of an element of boron (B), aluminum (Al), scandium (Sc), manganese (Mn), strontium (Sr), and/or indium (In) in a thickness direction thereof. The switching device and/or a semiconductor device may exhibit stable switching characteristics while having a low off-current value (leakage current value).

Abstract: Provided are a chalcogen compound having ovonic threshold switching characteristics, and a switching device, a semiconductor device, and/or a semiconductor apparatus which include the chalcogen compound. The chalcogen compound includes five or more elements and may have stable switching characteristics with a low off-current value (leakage current value). The chalcogen compound includes: selenium (Se) and tellurium (Te); a first element comprising at least one of indium (In), aluminum (Al), strontium (Sr), and calcium (Ca); and a second element including germanium (Ge) and/or tin (Sn), and may further include at least one of arsenic (As), antimony (Sb), and bismuth (Bi).

Abstract: A memory device according to an embodiment includes a memory cell array; a timing circuit configured to generate a first clock signal and a second clock signal, the second clock signal having a frequency that is i-times the frequency of the first clock signal; a command decoder configured to receive On-The-Fly (OTF) data including a plurality of OTF bits; a receiver configured to receive input data, configured to sample the input data based on the first clock signal, and configured to generate a first signal based on the sampled input data; a deserializer configured to generate a first deserialized signal from the first signal based on the second clock signal; a data pattern generator configured to generate a pattern signal based on the first deserialized signal and the OTF data based on the second clock signal; and a decoder configured to transmit the pattern signal to the memory cell array, where i is a natural number greater than or equal to 2.

Abstract: An operating method of a self-selecting memory device, includes an operation of applying a first write pulse corresponding to a first state to a first memory cell during a first pulse width, and an operation of applying a second write pulse corresponding to a second state to a second memory cell during a second pulse width, wherein the first write pulse and the second write pulse have substantially opposite polarities, wherein the first pulse width is longer than the second pulse width.

Abstract: A chalcogen compound layer exhibiting ovonic threshold switching characteristics, a switching device, a semiconductor device, and/or a semiconductor apparatus including the same are provided. The switching device and/or the semiconductor device may include two or more chalcogen compound layers having different energy band gaps. Alternatively, the switching device and/or semiconductor device may include a chalcogen compound layer having a concentration gradient of an element of boron (B), aluminum (Al), scandium (Sc), manganese (Mn), strontium (Sr), and/or indium (In) in a thickness direction thereof. The switching device and/or a semiconductor device may exhibit stable switching characteristics while having a low off-current value (leakage current value).

Abstract: A chalcogen compound layer exhibiting ovonic threshold switching characteristics, a switching device, a semiconductor device, and/or a semiconductor apparatus including the same are provided. The switching device and/or the semiconductor device may include two or more chalcogen compound layers having different energy band gaps. Alternatively, the switching device and/or semiconductor device may include a chalcogen compound layer having a concentration gradient of an element of boron (B), aluminum (Al), scandium (Sc), manganese (Mn), strontium (Sr), and/or indium (In) in a thickness direction thereof. The switching device and/or a semiconductor device may exhibit stable switching characteristics while having a low off-current value (leakage current value).

Abstract: A resistive memory device includes a first conductive line extending in a first horizontal direction on a substrate, a plurality of second conductive lines separated from the first conductive line in a vertical direction and extending in a second horizontal direction intersecting with the first horizontal direction, on the substrate, a plurality of memory cells respectively connected between the first conductive line and one second conductive line selected from among the plurality of second conductive lines at a plurality of intersection points between the first conductive line and the plurality of second conductive lines, each of the plurality of memory cells including a selection device and a resistive memory pattern, and a bottom electrode shared by the plurality of memory cells, the bottom electrode having a variable thickness in the first horizontal direction, and including a top surface having a concave-convex shape.

Abstract: A variable resistance memory device includes a first conductive line extending on a substrate in a first horizontal direction; a second conductive line extending on the first conductive line in a second horizontal direction perpendicular to the first horizontal direction; and a memory cell at an intersection between the first conductive line and the second conductive line, the memory cell including a selection element and a variable resistor, wherein the variable resistor includes a first variable resistance layer having a senary component represented by CaGedSbcTedAeXf, in which A and X are each a group 13 element different from each other, and 1?a?18, 13?b?26, 15?c?30, 35?d?55, 0.1?e?8, 0.1?f?8, and a+b+c+d+e+f=100.

Abstract: A semiconductor device includes a semiconductor substrate, a peripheral device on the semiconductor substrate, a lower insulating structure on the semiconductor substrate and covering the peripheral device, a first conductive line on the lower insulating structure, a memory cell structure on the first conductive line, and a second conductive line on the memory cell structure. The memory cell structure may include an information storage material pattern and a selector material pattern on the lower insulating structure in a vertical direction. The selector material pattern may include a first selector material layer including a first material and a second selector material layer including a second material. The second selector material layer may have a threshold voltage drift higher than that of the first material. The second selector material layer may have a second width narrower than a first width of the first selector material layer.

Abstract: A resistive memory device including a resistive memory pattern; and a selection element pattern electrically connected to the resistive memory pattern, the selection element pattern including a chalcogenide switching material and at least one metallic material, the chalcogenide switching material including germanium, arsenic, and selenium, and the at least one metallic material including aluminum, strontium, or indium, wherein the selection element pattern includes an inhomogeneous material layer in which content of the at least one metallic material in the selection element pattern is variable according to a position within the selection element pattern.

Abstract: Provided are a chalcogen compound having ovonic threshold switching characteristics, and a switching device, a semiconductor device, and/or a semiconductor apparatus which include the chalcogen compound. The chalcogen compound includes five or more elements and may have stable switching characteristics with a low off-current value (leakage current value). The chalcogen compound includes: selenium (Se) and tellurium (Te); a first element comprising at least one of indium (In), aluminum (Al), strontium (Sr), and calcium (Ca); and a second element including germanium (Ge) and/or tin (Sn), and may further include at least one of arsenic (As), antimony (Sb), and bismuth (Bi).

Abstract: A chalcogen compound layer exhibiting ovonic threshold switching characteristics, a switching device, a semiconductor device, and/or a semiconductor apparatus including the same are provided. The switching device and/or the semiconductor device may include two or more chalcogen compound layers having different energy band gaps. Alternatively, the switching device and/or semiconductor device may include a chalcogen compound layer having a concentration gradient of an element of boron (B), aluminum (Al), scandium (Sc), manganese (Mn), strontium (Sr), and/or indium (In) in a thickness direction thereof. The switching device and/or a semiconductor device may exhibit stable switching characteristics while having a low off-current value (leakage current value).

Abstract: A semiconductor device includes a semiconductor substrate, a peripheral device on the semiconductor substrate, a lower insulating structure on the semiconductor substrate and covering the peripheral device, a first conductive line on the lower insulating structure, a memory cell structure on the first conductive line, and a second conductive line on the memory cell structure. The memory cell structure may include an information storage material pattern and a selector material pattern on the lower insulating structure in a vertical direction. The selector material pattern may include a first selector material layer including a first material and a second selector material layer including a second material. The second selector material layer may have a threshold voltage drift higher than that of the first material. The second selector material layer may have a second width narrower than a first width of the first selector material layer.

Abstract: A semiconductor processing system may include a substrate pedestal. The system may also include at least one fluid channel having a delivery portion configured to deliver a temperature controlled fluid to the substrate pedestal, and having a return portion configured to return the temperature controlled fluid from the substrate pedestal. The system may also include a heater coupled with the delivery portion of the at least one fluid channel. The system may also include a temperature measurement device coupled with the return portion of the at least one fluid channel, and the temperature measurement device may be communicatively coupled with the heater.

Abstract: A semiconductor device includes a lower insulating structure covering a circuit element on a semiconductor substrate and an upper structure on the lower insulating structure. The upper structure includes a memory cell structure between first and second conductive lines. The first conductive lines extend in a first horizontal direction, and the second conductive lines extend in a second horizontal direction. The memory cell structure includes at least three electrode patterns, a data storage material pattern, and a selector material pattern overlapping in a vertical direction. The selector material pattern includes a threshold switching material and a metal material. The threshold switching material includes germanium (Ge), arsenic (As), and selenium (Se), and the metal material includes at least one of tungsten (W), titanium (Ti), aluminum (Al), and copper (Cu). A content of the metal material is greater than 0 atomic % and less than 2 atomic %.

Abstract: A resistive memory device includes a first conductive line extending in a first horizontal direction on a substrate, a plurality of second conductive lines separated from the first conductive line in a vertical direction and extending in a second horizontal direction intersecting with the first horizontal direction, on the substrate, a plurality of memory cells respectively connected between the first conductive line and one second conductive line selected from among the plurality of second conductive lines at a plurality of intersection points between the first conductive line and the plurality of second conductive lines, each of the plurality of memory cells including a selection device and a resistive memory pattern, and a bottom electrode shared by the plurality of memory cells, the bottom electrode having a variable thickness in the first horizontal direction, and including a top surface having a concave-convex shape.

Abstract: A semiconductor processing system may include a substrate pedestal. The system may also include at least one fluid channel having a delivery portion configured to deliver a temperature controlled fluid to the substrate pedestal, and having a return portion configured to return the temperature controlled fluid from the substrate pedestal. The system may also include a heater coupled with the delivery portion of the at least one fluid channel. The system may also include a temperature measurement device coupled with the return portion of the at least one fluid channel, and the temperature measurement device may be communicatively coupled with the heater.