Abstract: A display device includes a substrate including a pixel region and a peripheral region. A plurality of pixels is disposed in the pixel region of the substrate. Each of the plurality of pixels includes a light emitting element. Data lines and scan lines are connected to each of the plurality of pixels. A power line is configured to supply power to the plurality of pixels. The power line includes a plurality of first conductive lines and a plurality of second conductive lines intersecting the plurality of first conductive lines. The plurality of second conductive lines is arranged in a region between adjacent light emitting elements of the plurality of pixels. At least some of the plurality of second conductive lines extend in a direction oblique to a direction of extension of the data lines or the scan lines.

Abstract: A semiconductor package includes a substrate; a substrate pad on the substrate; a first semiconductor chip and a second semiconductor chip on the substrate; a connective terminal between the substrate pad and the first semiconductor chip and between the substrate pad and the second semiconductor chip; a dummy pad on the substrate, and spaced apart from the substrate pad, wherein the dummy pad is between the first semiconductor chip and the second semiconductor chip; and an underfill material layer interposed between the substrate and the first semiconductor chip and between the substrate and the second semiconductor chip, wherein the dummy pad and the substrate pad include a same material.

Abstract: A semiconductor device includes an insulating layer on a substrate; a via extending from within the substrate and extending through one face of the substrate and a bottom face of a trench defined in the insulating layer such that a portion of a sidewall and a top face of the via are exposed through the substrate; and a pad contacting the exposed portion of the sidewall and the top face of the via. The pad fills the trench. The insulating layer includes a passivation layer on the substrate, and a protective layer is on the passivation layer. An etch stop layer is absent between the passivation layer and the protective layer. A vertical level of a bottom face of the trench is higher than a vertical level of one face of the substrate and is lower than a vertical level of a top face of the passivation layer.

Abstract: A method of manufacturing a semiconductor package includes forming a plurality of trenches at a first surface of a silicon substrate, forming a conductive pad inside each of the plurality of trenches, forming a redistribution layer on the first surface of the silicon substrate, forming an external connection terminal on a first surface of the redistribution layer, removing the silicon substrate to expose each conductive pad, mounting a semiconductor chip to be connected to the conductive pads, and forming an encapsulant to cover at least one surface of the semiconductor chip.

Abstract: A light emitting diode display device includes a display board comprising a plurality of unit pixels, a drive circuit board including a plurality of drive circuit regions corresponding to the plurality of unit pixels, and a plurality of bumps interposed between the plurality of unit pixels and the plurality of drive circuit regions. The plurality of unit pixels comprises a first unit pixel including a first P electrode. The plurality of drive circuit regions comprises a first drive circuit region corresponding to the first unit pixel and a first pad connected to a first drive transistor, the plurality of bumps includes a first solder in contact with the first pad, and a first bump on the first solder and including a first filler in contact with the first P electrode, the first solder includes at least one of tin and silver, and the first filler includes copper or nickel.

Abstract: A method of manufacturing a semiconductor package includes forming a plurality of trenches at a first surface of a silicon substrate, forming a conductive pad inside each of the plurality of trenches, forming a redistribution layer on the first surface of the silicon substrate, forming an external connection terminal on a first surface of the redistribution layer, removing the silicon substrate to expose each conductive pad, mounting a semiconductor chip to be connected to the conductive pads, and forming an encapsulant to cover at least one surface of the semiconductor chip.

Abstract: A light emitting diode display device includes a display board comprising a plurality of unit pixels, a drive circuit board including a plurality of drive circuit regions corresponding to the plurality of unit pixels, and a plurality of bumps interposed between the plurality of unit pixels and the plurality of drive circuit regions. The plurality of unit pixels comprises a first unit pixel including a first P electrode. The plurality of drive circuit regions comprises a first drive circuit region corresponding to the first unit pixel and a first pad connected to a first drive transistor, the plurality of bumps includes a first solder in contact with the first pad, and a first bump on the first solder and including a first filler in contact with the first P electrode, the first solder includes at least one of tin and silver, and the first filler includes copper or nickel.

Abstract: A stack of semiconductor chips, a semiconductor device, and a method of manufacturing are disclosed. The stack of semiconductor chips may comprise a first chip of the stack, a second chip of the stack over the first chip, conductive bumps, a homogeneous integral underfill material, and a molding material. The conductive bumps may extend between an upper surface of the first chip and a lower surface of the second chip. The homogeneous integral underfill material may be interposed between the first chip and the second chip, encapsulate the conductive bumps, and extend along sidewalls of the second chip. The homogeneous integral underfill material may have an upper surface extending in a direction parallel to an upper surface of the second chip and located adjacent the upper surface of the second chip.

Abstract: A semiconductor package and a method for fabricating the same are provided. The semiconductor package includes a wafer, a plurality of semiconductor chips each having a connection pad and being stacked on the wafer, resin layers formed to expose top surfaces of the connection pads and to cover lateral surfaces and top surfaces of the semiconductor chips, through lines formed in at least one side of opposite sides of each of the semiconductor chips, to be spaced apart from the semiconductor chips, and to extend in a first direction, and redistribution lines arranged between the through lines, formed to extend in a second direction on the resin layers, and connected to the connection pads, wherein the through lines and the redistribution lines include barrier layers formed on lateral surfaces and bottom surfaces of the through lines and the redistribution lines, and conductive layers formed on the barrier layers.

Abstract: A stack package usable in a three-dimensional (3D) system-in-package (SIP) includes a first semiconductor chip, a second semiconductor chip, and a supporter. The first semiconductor chip includes a through silicon via (TSV), and the second semiconductor chip is stacked on the first semiconductor chip and is electrically connected to the first semiconductor chip through the TSV of the first semiconductor chip. The supporter is attached onto the first semiconductor chip so as to be spaced apart from an edge of the second semiconductor chip.

Abstract: A stack of semiconductor chips, a semiconductor device, and a method of manufacturing are disclosed. The stack of semiconductor chips may comprise a first chip of the stack, a second chip of the stack over the first chip, conductive bumps, a homogeneous integral underfill material, and a molding material. The conductive bumps may extend between an upper surface of the first chip and a lower surface of the second chip. The homogeneous integral underfill material may be interposed between the first chip and the second chip, encapsulate the conductive bumps, and extend along sidewalls of the second chip. The homogeneous integral underfill material may have an upper surface extending in a direction parallel to an upper surface of the second chip and located adjacent the upper surface of the second chip.

Abstract: A stack of semiconductor chips, a semiconductor device, and a method of manufacturing are disclosed. The stack of semiconductor chips may comprise a first chip of the stack, a second chip of the stack over the first chip, conductive bumps, a homogeneous integral underfill material, and a molding material. The conductive bumps may extend between an upper surface of the first chip and a lower surface of the second chip. The homogeneous integral underfill material may be interposed between the first chip and the second chip, encapsulate the conductive bumps, and extend along sidewalls of the second chip. The homogeneous integral underfill material may have an upper surface extending in a direction parallel to an upper surface of the second chip and located adjacent the upper surface of the second chip.

Abstract: A method for manufacturing a tape wiring board in accordance with the present invention may employ an imprinting process in forming a wiring pattern, thereby reducing the number of processes for manufacturing a tape wiring board and allowing the manufacturing process to proceed in a single production line. Therefore, the manufacturing time and cost may be reduced. A profile of the wiring pattern may be determined by the shape of an impression pattern of a mold. This may establish the top width of inner and outer leads and incorporate tine pad pitch. Although ILB and OLB process may use an NCP, connection reliability may be established due to the soft and elastic wiring pattern.

Abstract: A stack of semiconductor chips, a semiconductor device, and a method of manufacturing are disclosed. The stack of semiconductor chips may comprise a first chip of the stack, a second chip of the stack over the first chip, conductive bumps, a homogeneous integral underfill material, and a molding material. The conductive bumps may extend between an upper surface of the first chip and a lower surface of the second chip. The homogeneous integral underfill material may be interposed between the first chip and the second chip, encapsulate the conductive bumps, and extend along sidewalls of the second chip. The homogeneous integral underfill material may have an upper surface extending in a direction parallel to an upper surface of the second chip and located adjacent the upper surface of the second chip.

Abstract: Provided are camera modules capable of effectively shielding electromagnetic (EM) waves and methods of fabricating the same. A method of fabricating a camera module includes, preparing a first wafer including an array of lens units. Then, a second wafer including an array of image sensor CSPs (chip-scale packages) is prepared. Each of the image sensor CSPs includes an image sensor chip corresponding to one of the lens units. The first wafer is stacked on the second wafer. The first wafer and the second wafer are cut to form a trench exposing the top surface of the image sensor chip at the interface between adjacent lens units. The trench is filled with a first material used for forming a housing. The first material and the image sensor chip are cut at the interface between the adjacent lens units.

Abstract: A stack package usable in a three-dimensional (3D) system-in-package (SIP) includes a first semiconductor chip, a second semiconductor chip, and a supporter. The first semiconductor chip includes a through silicon via (TSV), and the second semiconductor chip is stacked on the first semiconductor chip and is electrically connected to the first semiconductor chip through the TSV of the first semiconductor chip. The supporter is attached onto the first semiconductor chip so as to be spaced apart from an edge of the second semiconductor chip.

Abstract: A method for manufacturing a tape wiring board in accordance with the present invention may employ an imprinting process in forming a wiring pattern, thereby reducing the number of processes for manufacturing a tape wiring board and allowing the manufacturing process to proceed in a single production line. Therefore, the manufacturing time and cost may he reduced. A profile of the wiring pattern may be determined by the shape of an impression pattern of a mold. This may establish the top width of inner and outer leads and incorporate tine pad pitch. Although ILB and OLB process may use an NCP, connection reliability may be established due to the soft and elastic wiring pattern.

Abstract: A camera module includes an image sensor chip, a lens structure, a transparent substrate, an adhesive portion, and a light blocking layer. The image sensor chip includes a light receiving area and a circuit area. The lens structure is positioned on the image sensor chip and configured to allow light to enter the image sensor chip. The transparent substrate is positioned between the image sensor chip and the lens structure, the transparent substrate allowing light from the lens structure to enter the light receiving area. The adhesive portion attaches the image sensor chip and the transparent substrate, and covers the circuit area. The light blocking layer is attached to the transparent substrate to block light from entering the circuit area.

Abstract: A method for manufacturing a tape wiring board in accordance with the present invention may employ an imprinting process in forming a wiring pattern thereby reducing the number of processes for manufacturing a tape wiring board and allowing the manufacturing process to proceed in a single production line. Therefore, the manufacturing time and cost may be reduced. A profile of the wiring pattern may be determined by the shape of an impression pattern of a mold. This may establish the top width of inner and outer leads and incorporate fine pad pitch. Although ILB and OLB process may use an NCP, connection reliability may be established due to the soft and elastic wiring pattern.

Abstract: An image sensor package, a method of manufacturing the same, and an image sensor module including the image sensor package are provided. In the image sensor package, an image sensor chip is installed onto a depression of a transmissive substrate. An adhesive bonds the image sensor chip to the transmissive substrate and seals an Active Pixel Sensor (APS) on the image sensor chip, protecting it from fine particle contamination. An IR cutting film is disposed on the transmissive substrate to minimize the height of the image sensor package. The image sensor package is electrically connected to external connection pads in the depression. Consequently, the image sensor package has a minimum height, is not susceptible to particle contamination, and does not require expensive alignment processes during manufacturing.