Patents by Inventor Chunhyung Chung

Chunhyung Chung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
    Publication number: 20170243973
    Abstract: A semiconductor device including a semiconductor substrate including a trench, the semiconductor substrate having a crystal structure; and an insulating layer covering an inner sidewall of the trench, wherein the inner sidewall of the trench has at least one plane included in a {320} family of planes of the crystal structure or at least one plane similar to the {320} family of planes.
    Type: Application
    Filed: December 28, 2016
    Publication date: August 24, 2017
    Inventors: Sungsam LEE, Junsoo KIM, Hyoshin AHN, Satoru YAMADA, Joohyun JEON, MoonYoung JEONG, Chunhyung CHUNG, Min Hee CHO, Kyo-Suk CHAE, Eunae CHOI
  • Method of forming dielectric including dysprosium and scandium by atomic layer deposition and integrated circuit device including the dielectric layer
    Patent number: 8105930
    Abstract: In one embodiment, the method of forming a dielectric layer includes supplying a first precursor at a temperature less than 400 degrees Celsius to a chamber including a substrate. The first precursor includes dysprosium. A first reaction gas is supplied to the chamber to react with the first precursor. A second precursor is supplied at a temperature less than 400 degrees Celsius to the chamber, and the second precursor includes scandium. A second reaction gas is supplied to the chamber to react with the second precursor.
    Type: Grant
    Filed: May 28, 2008
    Date of Patent: January 31, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hoonsang Choi, Bongjin Kuh, Sunjung Kim, Youngsun Kim, Seunghwan Lee, Sangwook Lim, Chunhyung Chung
  • Nonvolatile Memory Devices Having Charge-Trap Layers Therein with Relatively High Election Affinity
    Publication number: 20100052041
    Abstract: Provided is a nonvolatile memory device. The nonvolatile memory device may include a tunnel insulating layer on a semiconductor substrate; a charge trap layer disposed on the tunnel insulating layer and having an electron affinity greater than a silicon nitride layer; a barrier insulating layer on the charge trap layer; a blocking insulating layer on the barrier insulating layer; and a gate electrode on the blocking insulating layer. An electron affinity of the barrier insulating layer is smaller than an electron affinity of the blocking insulating layer.
    Type: Application
    Filed: August 31, 2009
    Publication date: March 4, 2010
    Inventors: Junkyu Yang, Young-Geun Park, Chunhyung Chung, EunSok Choi, Seon-Ho Jo, Hanmei Choi, Young-Sun Kim
  • Method of forming dielectric including dysprosium and scandium by atomic layer deposition and integrated circuit device including the dielectric layer
    Publication number: 20090039415
    Abstract: In one embodiment, the method of forming a dielectric layer includes supplying a first precursor at a temperature less than 400 degrees Celsius to a chamber including a substrate. The first precursor includes dysprosium. A first reaction gas is supplied to the chamber to react with the first precursor. A second precursor is supplied at a temperature less than 400 degrees Celsius to the chamber, and the second precursor includes scandium. A second reaction gas is supplied to the chamber to react with the second precursor.
    Type: Application
    Filed: May 28, 2008
    Publication date: February 12, 2009
    Inventors: Hoonsang Choi, Bongjin Kuh, Sunjung Kim, Youngsun Kim, Seunghwan Lee, Sangwook Lim, Chunhyung Chung