Abstract: A semiconductor device includes a first wafer comprising a first portion of a seal ring structure within a body of the first wafer. The semiconductor device includes a second wafer comprising a second portion of the seal ring structure within a body of the second wafer. The second wafer is affixed to the first wafer such that the second portion of the seal ring structure is on the first portion of the seal ring structure. The semiconductor device includes a trench structure comprising a first trench in the first wafer and a second trench in the second wafer, where the first trench and the second trench are on a same side of the seal ring structure.

Abstract: A semiconductor device includes a first wafer and a second wafer. The semiconductor device includes a seal ring structure comprising a first metal structure in a body of the first wafer, a second metal structure in the body of the first wafer, a third metal structure in a body of the second wafer, and a metal bonding structure including a first set of metal elements coupling the first metal structure and the third metal structure through an interface between the first wafer and the second wafer, and a second set of metal elements coupling the second metal structure and the third metal structure through the interface between the first wafer and the second wafer.

Abstract: A semiconductor device includes a first wafer comprising a first portion of a seal ring structure within a body of the first wafer. The semiconductor device includes a second wafer comprising a second portion of the seal ring structure within a body of the second wafer. The second wafer is affixed to the first wafer such that the second portion of the seal ring structure is on the first portion of the seal ring structure. The semiconductor device includes a trench structure comprising a first trench in the first wafer and a second trench in the second wafer, where the first trench and the second trench are on a same side of the seal ring structure.

Abstract: A semiconductor device includes a first wafer and a second wafer. The semiconductor device includes a seal ring structure comprising a first metal structure in a body of the first wafer, a second metal structure in the body of the first wafer, a third metal structure in a body of the second wafer, and a metal bonding structure including a first set of metal elements coupling the first metal structure and the third metal structure through an interface between the first wafer and the second wafer, and a second set of metal elements coupling the second metal structure and the third metal structure through the interface between the first wafer and the second wafer.

Abstract: Some implementations described herein include a complementary metal oxide semiconductor image sensor device and techniques to form the complementary metal oxide semiconductor image sensor device. The complementary metal oxide semiconductor image sensor device includes a includes a first array of photodiodes stacked over a second array of photodiodes. A polarization structure is between the first array of photodiodes and the second array of photodiodes. Signaling generated by the first array of photodiodes (e.g., signaling corresponding to unpolarized light waves) may be multiplexed with signaling generated by the second array of photodiodes (e.g., signaling corresponding to polarized light waves). The complementary metal oxide semiconductor image sensor device further includes a filter structure that filters visible light waves and near infrared light waves amongst the first array of photodiodes and the second array of photodiodes.

Abstract: Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a first wafer including a first metal structure within a body of the first wafer. The semiconductor structure also includes a second wafer including a second metal structure within a body of the second wafer, where the first wafer is coupled to the second wafer at an interface. The semiconductor structure further includes a metal bonding structure coupled to the first metal structure and the second metal structure and extending through the interface.

Abstract: A CMOS image sensor includes a unit pixel array including a photodiode array, a color filter array, a micro-lens array, and a grid isolation structure laterally separating adjacent color filters. The grid isolation structure includes a first low-n grid, a second low-n grid underlying the first low-n grid, and a metal grid within the second low-n grid, the first low-n grid being narrower than the second low-n grid. The color filter array includes color filter matrixes, all color filter matrixes have the same arrangement pattern. Sizes of color filters in each color filter matrix vary depending on locations of the color filters in the color filter matrix. In an edge portion, a distance between a center of a color filter matrix and a center of a corresponding unit pixel matrix in plan view varies depending on a location of the unit pixel matrix in the CMOS image sensor.

Abstract: Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a first wafer including a first metal structure within a body of the first wafer. The semiconductor structure also includes a second wafer including a second metal structure within a body of the second wafer, where the first wafer is coupled to the second wafer at an interface. The semiconductor structure further includes a metal bonding structure coupled to the first metal structure and the second metal structure and extending through the interface.

Abstract: Some implementations described herein provide an optoelectronic device and methods of formation. The optoelectronic device is fabricated using a series of operations that includes a patterning operation using a layer of a negative photoresist material, followed by a single dry etch operation, a single wet strip operation, and a single wet etch operation. The series of operations may include a reduced number of operations relative to another series of operations that include a patterning operation using a layer of a positive photoresist material. Through the reduced number of operations, handling-induced damage to the device may be reduced. Additionally, the high absorption structure may include a quantum efficiency that is greater relative to another quantum efficiency of another high absorption structure formed through the series of operations that include the patterning operation using the layer of the positive photoresist material.

Abstract: A pixel sensor array of an image sensor device described herein may include a deep trench isolation (DTI) structure that includes a plurality of DTI portions that extend into a substrate of the image sensor device. Two or more subsets of the plurality of DTI portions may extend around photodiodes of a pixel sensor of the pixel sensor array, and may extend into the substrate to different depths. The different depths enable the photocurrents generated by the photodiodes to be binned and used to generate unified photocurrent. In particular, the different depths enable photons to intermix in the photodiodes, which enables quadradic phase detection (QPD) binning for increased PDAF performance. The increased PDAF performance may include increased autofocus speed, increased high dynamic range, increased quantum efficiency (QE), and/or increased full well conversion (FWC), among other examples.

Abstract: A semiconductor device includes a substrate, a gate structure, a first doped region and a second doped region. The substrate has a plurality of recesses therein. A gate structure covers the plurality of recesses and a surface of the substrate between the plurality of recesses. The gate structure includes a gate dielectric layer and a gate conductive layer. The gate dielectric layer covers bottom surfaces and sidewalls of the plurality of recesses and the surface of the substrate between the plurality of recesses. The gate conductive layer is formed on the gate dielectric layer, fills in the plurality of recesses and covers the surface of the substrate between the plurality of recesses. The first doped region and the second doped region are located at two sides of the gate structure.

Abstract: A method of making a semiconductor image sensor includes forming a photodiode in a substrate. The method further includes forming a recess in the substrate. The method further includes depositing a sacrificial material in the recess. The method further includes forming an interconnect structure over the sacrificial material. The method further includes etching a plurality of trenches in the interconnect structure. The method further includes removing the sacrificial material by passing an etchant through the plurality of trenches.

Abstract: A semiconductor device and a method for manufacturing the semiconductor device are provided. The semiconductor device comprises a substrate and a wafer disposed on the substrate. The wafer includes a p-doped layer disposed on the substrate; a first diode disposed on the p-doped layer; a second diode disposed on the p-doped layer; a third diode disposed on the p-doped layer; and a dielectric layer disposed on the substrate and covering the first, second, and third diodes. The first, second, and third diodes are disposed side by side.

Abstract: A semiconductor image sensor includes a pixel. The pixel includes a first substrate; and a photodiode in the first substrate. The semiconductor image sensor further includes an interconnect structure electrically connected to the pixel. The semiconductor image sensor further includes a reflection structure between the interconnect and the photodiode, wherein the reflection structure is configured to reflect light passing through the photodiode back toward the photodiode.

Abstract: A semiconductor image sensing structure includes a substrate, an isolation structure, an anti-reflection structure, at least one optical element and a transistor. The substrate has at least one photodiode region. The isolation structure is disposed in the substrate and surrounds the photodiode region. The anti-reflection structure covers the photodiode region. The optical element is disposed over the anti-reflection structure and corresponds to the photodiode region. The transistor is disposed under the photodiode region.

Abstract: An image sensor includes a substrate having first and second surfaces opposite to each other, an image pixel area, and a black level calibration (BLC) area adjacent to the image pixel area. The BLC area includes a dark current sensing circuit including photo diodes disposed in the substrate, a first seal ring disposed over the second surface and surrounding the image pixel area in plan view, a second seal ring disposed over the second surface and surrounding the image pixel area in plan view such that the dark current sensing circuit is disposed between the first and second seal rings, an opaque cover disposed over the first surface and covering the dark current sensing circuit, the first and second seal rings, and one or more first trench isolation structures extending from the first surface to an inside the substrate and disposed between the first seal ring and the opaque cover.

Abstract: Provided is an image sensor and a method of forming the same. The image sensor includes a first substrate having a first surface and a second surface opposite to each other; a plurality of photodetectors, disposed in the first substrate; and a plurality of color filters, disposed on the second surface of the first substrate and respectively corresponding to the plurality of photodetectors. The plurality of color filters are composed of a plurality of PIN diodes, and the plurality of PIN diodes are configured to absorb light of different wavelength ranges by applying different bias voltages.

Abstract: A memory device and an operation method thereof are disclosed. The memory device includes a P-well region, a common source line, a ground selection line, at least one dummy ground selection line, a plurality of word lines, at least one dummy string selection line, a string selection line, at least one bit line and at least one memory string. The gates of a plurality of memory cells of the memory string are connected to the word lines. The operation method includes the following steps. Performing a read operation and applying a read voltage on the selected word line. Applying a pass voltage on other unselected word lines and the ground selection lines, etc. Before ending of the read operation, firstly decreasing voltages of the string selection line and the dummy string selection line in advance, then increasing voltage of the bit line.

Abstract: A semiconductor device includes a first wafer and a second wafer. The semiconductor device includes a seal ring structure comprising a first metal structure in a body of the first wafer, a second metal structure in the body of the first wafer, a third metal structure in a body of the second wafer, and a metal bonding structure including a first set of metal elements coupling the first metal structure and the third metal structure through an interface between the first wafer and the second wafer, and a second set of metal elements coupling the second metal structure and the third metal structure through the interface between the first wafer and the second wafer.

Abstract: A semiconductor device includes a first wafer and a second wafer. The semiconductor device includes a seal ring structure comprising a first metal structure in a body of the first wafer, a second metal structure in the body of the first wafer, a third metal structure in a body of the second wafer, and a metal bonding structure including a first set of metal elements coupling the first metal structure and the third metal structure through an interface between the first wafer and the second wafer, and a second set of metal elements coupling the second metal structure and the third metal structure through the interface between the first wafer and the second wafer.