Patents by Inventor Chunlin Liang
Chunlin Liang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220033321Abstract: An exemplary solid waste treatment system can be provided which can include a storage device, an intelligent aerobic fermentation treatment device, a retaining wall-type fermentation area, and an aeration platform. The intelligent aerobic fermentation treatment device can include a traveling trolley, a lifting mechanism, a material pick-and-place mechanism, and a traveling bridge linearly moving in a direction away from the storage device towards the retaining wall-type fermentation area. The aeration platform can be arranged at the bottom of the retaining wall-type fermentation area. The traveling trolley linearly can move on the traveling bridge in a direction perpendicular to the direction away from the storage device towards the retaining wall-type fermentation area. The lifting mechanism can be mounted on the traveling trolley. The material pick-and-place mechanism can be suspended on the lifting mechanism to be raised and lowered in step with the raising and lowering of the lifting mechanism.Type: ApplicationFiled: October 29, 2019Publication date: February 3, 2022Inventors: Shufang ZHANG, Haixia ZHENG, Xinming WANG, Chunlin LIANG, Jingwei ZHANG,
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Patent number: 7223992Abstract: The invention relates to a trench filled with a thermally conducting material in a semiconductor substrate. In one embodiment, the semiconductor device has a trench defining a cell region, wherein a portion of the trench includes a thermally conducting material, and a contact to the thermally conducting material. The invention further relates to a semiconductor device and a method of forming a semiconductor device with an interlayer dielectric that is a thermally conducting material.Type: GrantFiled: January 11, 2006Date of Patent: May 29, 2007Assignee: Intel CorporationInventors: Chunlin Liang, Brian S. Doyle
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Patent number: 7187044Abstract: A method for making circuit device that includes a first transistor having a first metal gate electrode overlying a first gate dielectric on a first area of a semiconductor substrate. The first gate electrode has a work function corresponding to the work function of one of P-type silicon and N-type silicon. The circuit device also includes a second transistor coupled to the first transistor. The second transistor has a second metal gate electrode over a second gate dielectric on a second area of the semiconductor substrate. The second gate metal gate electrode has a work function corresponding to the work function of the other one of P-type silicon and N-type silicon.Type: GrantFiled: March 2, 2000Date of Patent: March 6, 2007Assignee: Intel CorporationInventors: Chunlin Liang, Gang Bai
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Patent number: 7067406Abstract: The invention relates to a method of forming a trench filled with a thermally conducting material in a semiconductor substrate. In one embodiment, the method includes filling a portion of the trench with a thermally conducting material and patterning a contact to the thermally conducting material. The invention also relates to a semiconductor device. In one embodiment, the semiconductor device has a trench defining a cell region, wherein a portion of the trench includes a thermally conducting material, and a contact to the thermally conducting material. The invention further relates to a semiconductor device and a method of forming a semiconductor device with an interlayer dielectric that is a thermally conducting material.Type: GrantFiled: July 31, 2003Date of Patent: June 27, 2006Assignee: Intel CorporationInventors: Chunlin Liang, Brian S. Doyle
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Publication number: 20060121710Abstract: The invention relates to a trench filled with a thermally conducting material in a semiconductor substrate. In one embodiment, the semiconductor device has a trench defining a cell region, wherein a portion of the trench includes a thermally conducting material, and a contact to the thermally conducting material. The invention further relates to a semiconductor device and a method of forming a semiconductor device with an interlayer dielectric that is a thermally conducting material.Type: ApplicationFiled: January 11, 2006Publication date: June 8, 2006Inventors: Chunlin Liang, Brian Doyle
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Patent number: 7045468Abstract: A MOSFET structure in which the channel region is contiguous with the semiconductor substrate while the source and drain junctions are substantially isolated from the substrate, includes a dielectric volume formed adjacent and subjacent to portions of the source and drain regions. In a further aspect of the invention, a process for forming an isolated junction in a bulk semiconductor includes forming a dielectric volume adjacent and subjacent to portions of the source and drain regions.Type: GrantFiled: August 21, 2003Date of Patent: May 16, 2006Assignee: Intel CorporationInventor: Chunlin Liang
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Patent number: 7022559Abstract: An insulated gate field effect transistor (FET) of a particular conductivity type, has as a gate electrode, a non-semiconductive material with a work function that approximates the work function of a semiconductive material that is doped to be of the same conductivity type. In a particular embodiment, an integrated circuit includes an n-channel FET having a tantalum-based gate electrode with a work function approximately the same as n-doped polysilicon, and a p-channel FET has a tantalum nitride-based gate electrode with a work function approximately the same as p-doped polysilicon.Type: GrantFiled: November 20, 2002Date of Patent: April 4, 2006Assignee: Intel CorporationInventors: John P. Barnak, Robert S. Chau, Chunlin Liang
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Patent number: 6998357Abstract: A method of forming a dielectric layer suitable for use as the gate dielectric layer of a metal-oxide-semiconductor field effect transistor (MOSFET) includes oxidizing the surface of a silicon substrate, forming a metal layer over the oxidized surface, and reacting the metal with the oxidized surface to form a substantially intrinsic layer of silicon superjacent the substrate, wherein at least a portion of the silicon layer may be an epitaxial silicon layer, and a metal oxide layer superjacent the silicon layer. In a further aspect of the present invention, an integrated circuit includes a plurality of MOSFETs, wherein various ones of the plurality of transistors have metal oxide gate dielectric layers and substantially intrinsic silicon layers subjacent the metal oxide dielectric layers.Type: GrantFiled: August 22, 2003Date of Patent: February 14, 2006Assignee: Intel CorporationInventors: Gang Bai, David B. Fraser, Brian S. Doyle, Peng Cheng, Chunlin Liang
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Publication number: 20050087820Abstract: A method of forming a dielectric layer suitable for use as the gate dielectric layer of a metal-oxide-semiconductor field effect transistor (MOSFET) includes oxidizing the surface of a silicon substrate, forming a metal layer over the oxidized surface, and reacting the metal with the oxidized surface to form a substantially intrinsic layer of silicon superjacent the substrate, wherein at least a portion of the silicon layer may be an epitaxial silicon layer, and a metal oxide layer superjacent the silicon layer. In a further aspect of the present invention, an integrated circuit includes a plurality of MOSFETs, wherein various ones of the plurality of transistors have metal oxide gate dielectric layers and substantially intrinsic silicon layers subjacent the metal oxide dielectric layers.Type: ApplicationFiled: August 22, 2003Publication date: April 28, 2005Inventors: Gang Bai, David Fraser, Brian Doyle, Peng Cheng, Chunlin Liang
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Patent number: 6879009Abstract: A method of fabricating integrated circuits includes forming MOSFETs with gate electrodes of a first composition, and sidewall spacers along laterally opposed sides of those gate electrodes, removing the gate electrodes of the first composition, and replacing those gate electrodes with a gate electrode structure having at least two layers of metal. In a further aspect of the present invention, complementary metal oxide semiconductor integrated circuits are fabricated by replacing n-channel transistor gate electrodes with gate electrodes having at least a first metal and a second metal, and further replacing the p-channel transistor gate electrodes with gate electrodes having a third metal and a fourth metal. The first and second metal combination includes, but is not limited to, TiN and Al. The third and fourth metal combination includes, but is not limited to, TaN and Ni; TaN and Pd; and TaN and Pt.Type: GrantFiled: October 6, 2003Date of Patent: April 12, 2005Assignee: Intel CorporationInventors: Jun-Fei Zheng, Chunlin Liang
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Patent number: 6794232Abstract: Insulated gate field effect transistors having gate electrodes with at least two layers of materials provide gate electrode work function values that are similar to those of doped polysilicon, eliminate the poly depletion effect and also substantially prevent impurity diffusion into the gate dielectric. Bi-layer stacks of relatively thick Al and thin TiN for n-channel FETs and bi-layer stacks of relatively thick Pd and thin TiN, or relatively thick Pd and thin TaN for p-channel FETs are disclosed. Varying the thickness of the thin TiN or TaN layers between a first and second critical thickness may be used to modulate the work function of the gate electrode and thereby obtain the desired trade-off between channel doping and drive currents in FETs.Type: GrantFiled: March 7, 2003Date of Patent: September 21, 2004Assignee: Intel CorporationInventors: Jun-Fei Zheng, Brian Doyle, Gang Bai, Chunlin Liang
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Patent number: 6790731Abstract: A method for creating insulated gate field effect transistors having gate electrodes with at least two layers of materials to provide gate electrode work function values that are similar to those of doped polysilicon, to eliminate the poly depletion effect, and to substantially prevent impurity diffusion into the gate dielectric. Depositing bi-layer stacks of relatively thick Al and thin TiN for n-channel FETs and bi-layer stacks of relatively thick Pd and thin TiN, or relatively thick Pd and thin TaN for p-channel FETs is disclosed. Varying the thickness of the thin TiN or TaN layers between a first and second critical thickness may be used to modulate the work function of the gate electrode and thereby obtain the desired trade-off between channel doping and drive currents in FETs.Type: GrantFiled: February 6, 2002Date of Patent: September 14, 2004Assignee: Intel CorporationInventors: Jun-Fei Zheng, Brian Doyle, Gang Bai, Chunlin Liang
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Patent number: 6743664Abstract: A method is provided including attaching an encapsulant to an integrated circuit (IC), forming a substrate from at least one layer of dielectric, attaching at least one electrical contact to the substrate, attaching a first surface of the substrate to the encapsulant so that the substrate is connected to the IC, attaching an electrical element to a second surface of the substrate, and electronically connecting the first surface of the substrate and the second surface of the substrate.Type: GrantFiled: December 6, 2001Date of Patent: June 1, 2004Assignee: Intel CorporationInventors: Chunlin Liang, Larry Eugene Mosley, Chun Mu
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Publication number: 20040065903Abstract: A method of fabricating integrated circuits includes forming MOSFETs with gate electrodes of a first composition, and sidewall spacers along laterally opposed sides of those gate electrodes, removing the gate electrodes of the first composition, and replacing those gate electrodes with a gate electrode structure having at least two layers of metal. In a further aspect of the present invention, complementary metal oxide semiconductor integrated circuits are fabricated by replacing n-channel transistor gate electrodes with gate electrodes having at least a first metal and a second metal, and further replacing the p-channel transistor gate electrodes with gate electrodes having a third metal and a fourth metal. The first and second metal combination includes, but is not limited to, TiN and Al. The third and fourth metal combination includes, but is not limited to, TaN and Ni; TaN and Pd; and TaN and Pt.Type: ApplicationFiled: October 6, 2003Publication date: April 8, 2004Applicant: Intel CorporationInventors: Jun-Fei Zheng, Chunlin Liang
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Publication number: 20040038533Abstract: A MOSFET structure in which the channel region is contiguous with the semiconductor substrate while the source and drain junctions are substantially isolated from the substrate, includes a dielectric volume formed adjacent and subjacent to portions of the source and drain regions.Type: ApplicationFiled: August 21, 2003Publication date: February 26, 2004Inventor: Chunlin Liang
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Patent number: 6696333Abstract: A method of fabricating integrated circuits includes forming MOSFETs with gate electrodes of a first composition, and sidewall spacers along laterally opposed sides of those gate electrodes, removing the gate electrodes of the first composition, and replacing those gate electrodes with a gate electrode structure having at least two layers of metal. In a further aspect of the present invention, complementary metal oxide semiconductor integrated circuits are fabricated by replacing n-channel transistor gate electrodes with gate electrodes having at least a first metal and a second metal, and further replacing the p-channel transistor gate electrodes with gate electrodes having a third metal and a fourth metal. The first and second metal combination includes, but is not limited to, TiN and Al. The third and fourth metal combination includes, but is not limited to, TaN and Ni; TaN and Pd; and TaN and Pt.Type: GrantFiled: December 30, 1999Date of Patent: February 24, 2004Assignee: Intel CorporationInventors: Jun-Fei Zheng, Chunlin Liang
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Patent number: 6689702Abstract: A method of forming a dielectric layer suitable for use as the gate dielectric layer of a metal-oxide-semiconductor field effect transistor (MOSFET) includes oxidizing the surface of a silicon substrate, forming a metal layer over the oxidized surface, and reacting the metal with the oxidized surface to form a substantially intrinsic layer of silicon superjacent the substrate, wherein at least a portion of the silicon layer may be an epitaxial silicon layer, and a metal oxide layer superjacent the silicon layer. In a further aspect of the present invention, an integrated circuit includes a plurality of MOSFETs, wherein various ones of the plurality of transistors have metal oxide gate dielectric layers and substantially intrinsic silicon layers subjacent the metal oxide dielectric layers.Type: GrantFiled: November 25, 2002Date of Patent: February 10, 2004Assignee: Intel CorporationInventors: Gang Bai, David B. Fraser, Brian S. Doyle, Peng Cheng, Chunlin Liang
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Publication number: 20040022102Abstract: The invention relates to a method of forming a trench filled with a thermally conducting material in a semiconductor substrate. In one embodiment, the method includes filling a portion of the trench with a thermally conducting material and patterning a contact to the thermally conducting material. The invention also relates to a semiconductor device. In one embodiment, the semiconductor device has a trench defining a cell region, wherein a portion of the trench includes a thermally conducting material, and a contact to the thermally conducting material. The invention further relates to a semiconductor device and a method of forming a semiconductor device with an interlayer dielectric that is a thermally conducting material.Type: ApplicationFiled: July 31, 2003Publication date: February 5, 2004Inventors: Chunlin Liang, Brian S. Doyle
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Publication number: 20040018706Abstract: The invention relates to a method of forming a trench filled with a thermally conducting material in a semiconductor substrate. In one embodiment, the method includes filling a portion of the trench with a thermally conducting material and patterning a contact to the thermally conducting material. The invention also relates to a semiconductor device. In one embodiment, the semiconductor device has a trench defining a cell region, wherein a portion of the trench includes a thermally conducting material, and a contact to the thermally conducting material. The invention further relates to a semiconductor device and a method of forming a semiconductor device with an interlayer dielectric that is a thermally conducting material.Type: ApplicationFiled: July 9, 2003Publication date: January 29, 2004Inventors: Chunlin Liang, Brian S. Doyle
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Patent number: 6642557Abstract: A MOSFET structure in which the channel region is contiguous with the semiconductor substrate while the source and drain junctions are substantially isolated from the substrate, includes a dielectric volume formed adjacent and subjacent to portions of the source and drain regions. In a further aspect of the invention, a process for forming an isolated junction in a bulk semiconductor includes forming a dielectric volume adjacent and subjacent to portions of the source and drain regions.Type: GrantFiled: April 9, 1999Date of Patent: November 4, 2003Assignee: Intel CorporationInventor: Chunlin Liang