Abstract: A semiconductor device has an active area and a terminal area surrounding the active area and includes a base region, a plurality of annular subregions, an insulating layer provided with a plurality of insulating layer openings, and a first conductive layer. The plurality of annular subregions includes a first annular subregion in contact with the base region. The first annular subregion includes a plurality of annular structures in contact with each other. All the annular structures contact the first conductive layer through the corresponding insulating layer openings. The base region, the annular subregions, and the annular structures have a second conductivity type.

Abstract: A semiconductor device includes an insulated-gate bipolar transistor (IGBT) structure and a metal-oxide-semiconductor (MOS) transistor structure integrated in a wafer. The MOS transistor structure is connected in parallel with the IGBT structure. A thickness of a trench insulating layer in the MOS transistor structure is less than a thickness of a trench insulating layer in the IGBT structure.

Abstract: A semiconductor device includes a semiconductor layer with a first and second surface. The semiconductor layer includes: a source region and gate regions. The source region includes an N-type source region, a P-type body layer, and a carrier storage layer. Each gate region includes a gate oxide layer and polysilicon. The gate oxide layer surrounds a side wall and bottom of the polysilicon. The source region is arranged between adjacent gate regions and contacts the gate oxide layers. The gate oxide layer extends to a first depth. The bottom of the polysilicon is located at a second depth away from the first surface. A part of the gate oxide layer has a constant thickness in a transverse direction and another part gradually increases thickness in the transverse direction. The third depth is within a range of a depth where the first P-type body layer is located.

Abstract: The present disclosure has a substrate for power semiconductor packaging and a package containing such a substrate. The substrate includes: a first metal layer for contacting with a semiconductor device, a second metal layer for contacting with a heat dissipation device, an electrical insulation layer disposed between the first metal layer and the second metal layer, and a first graphene bulk layer disposed between the electrical insulation layer and the first metal layer, a first surface of the first graphene bulk layer is in contact with a first surface of the first metal layer, and a second surface of the first graphene bulk layer opposite to the first surface is in contact with a first surface of the electrical insulation layer. Compared to the conventional substrate, the novel substrate of the present disclosure exhibits much lower thermal resistance, higher mechanical strength, and enhanced corrosion resistance.

Abstract: A semiconductor device having cells is provided, with each cell including a gate. The device includes a gate pad, a gate busbar and gate lines. The busbar connects the gate pad to the gate lines, the gate lines connect the gate busbar to the gates of the cells, and each of the gate lines is disposed along a first axis. The gate busbar includes first portions each disposed along a second axis, and the second axis intersects with the first axis. The first portions are spaced apart from each other to divide the semiconductor device into emitter segments. Lengths of the emitter segments along the first axis changes with distances of the segments from the gate pad, so that gate signals arriving at the gates of the cells from the gate pad via the gate busbar and the gate lines are substantially consistent.

Abstract: A semiconductor device having cells is provided, with each cell including a gate. The device includes a gate pad, a gate busbar and gate lines. The busbar connects the gate pad to the gate lines, the gate lines connect the gate busbar to the gates of the cells, and each of the gate lines is disposed along a first axis. The gate busbar includes first portions each disposed along a second axis, and the second axis intersects with the first axis. The first portions are spaced apart from each other to divide the semiconductor device into emitter segments. Lengths of the emitter segments along the first axis changes with distances of the segments from the gate pad, so that gate signals arriving at the gates of the cells from the gate pad via the gate busbar and the gate lines are substantially consistent.

Abstract: A cell structure of an insulated gate bipolar transistor (IGBT) with a control gate and a carrier storage layer, is provided including: an N-type drift layer with a first surface, an active region on a second surface opposing the first and an N-type storage layer, a P-type body layer and an N-type doped layer sequentially stacked in the active region from the first to the second surface, gate trench bodies, each of which extends from the second to the first surface in a first direction perpendicular to the first surface and contacts the N-type drift layer, and each of the at least three gate trench bodies is a gate trench or a control gate trench. A sidewall of the gate trench is in contact with the active region, and a sidewall of the control gate trench is in contact with the P-type layer but not with the N-type layer.

Abstract: The disclosure provides power semiconductor modules and their assembling methods. The module includes a heat-dissipation contact area, a housing and a press-on element. One of the housing and the press-on element includes a rail portion, while the other includes a rail cooperating portion. The housing and the press-on element respectively includes a first limiting portion and a first limiting cooperating portion. The rail cooperating portion can be inserted into the rail portion and slides on the rail portion in the direction toward or away from the plane where the heat-dissipation contact area is located, so that the press-on element could move from the separation position to the mounted position connected with the housing. The rail portion can cooperate with the rail cooperating portion to prevent the press-on element from moving relative to the housing in the direction parallel to the plane where the heat-dissipation contact area is located.

Abstract: A semiconductor device and a manufacturing method thereof is provided. The device includes a semiconductor layer having a first and second surface opposing each other; a trench gate in the semiconductor layer, extends in a first direction parallel to the first and second surface, and from the first surface to an interior of the layer, and has a gate open end distant from the second surface; a source region of a first conductivity type and a channel region of a second conductivity type, orthographic projections of the source region and the channel region on the second surface at least partially overlap with each other in a depth direction of the trench gate, the source region having a source open end distant from the second surface, and the farther the source open end is from the second surface, the smaller a width of the source open end in the second direction.

Abstract: An IGBT chip having a ?-shape mixed gate structure includes a plurality of mixed gate units. Each of the mixed gate units includes a gate region and two active regions located at two sides of the gate region. The gate region includes a trench gate and a planar gate that is located on a surface of the gate region, and the planar gate is connected with the trench gate and formed a ?-shape mixed structure. In this way, the IGBT chip can have a significantly improved chip density, while retaining features of low power consumption and high current density of the trench gate and a feature of a wide safe operating area of the planar gate.

Abstract: A semiconductor device and a method for manufacturing the same is provided. The semiconductor device includes: a semiconductor body having a first surface and a second surface, the semiconductor body includes: a depletion region, a drift region having a first conductivity type, an island region having the first conductivity type, a buffer region having the first conductivity type, the drift region is more proximal to the first surface of the semiconductor body than the buffer region, the depletion region is located within the drift region, and the island region is located within the drift region, an ion concentration of the first conductivity type of the island region is higher than an ion concentration of the first conductivity type of the drift region.

Abstract: There is provided a power semiconductor device (1), comprising: a semiconductor substrate (2) comprising: a base layer (5) selectively provided at a first side of the semiconductor substrate, and wherein the base layer has a first conductivity type; a collector layer (3) provided at a second side of the semiconductor substrate, wherein the second side is opposite to the first side, and wherein the collector layer has the first conductivity type; and a drift layer (4) having a second conductivity type opposite to the first conductivity type, wherein the drift layer (4) is arranged between the collector layer (3) and the base layer (5); an active cell (15) provided in the semiconductor substrate (2), wherein the active cell (15) comprises an emitter region (7) which has the second conductivity type and an active base region (5-i) which is a part of the base layer (5); and an insulation trench (17) provided in the semiconductor substrate (2) and neighbouring the active cell (15), wherein: the insulation trench (

Abstract: This disclosure provides a design method for a radiator of a vehicle power module. The design method includes: selecting a plurality of specific values from the possible value ranges of the first distance D1, the second distance D2 and the radius R, respectively, to form different combinations of the plurality of specific values, performing simulation calculations on the different combinations, and obtaining a temperature rise ?Tj and a pressure drop ?Pf corresponding to each combination to form a plurality of samples; through a response surface method, fitting explicit functions of the temperature rise ?Tj and the pressure drop ?Pf with the first distance D1, the second distance D2 and the radius R as dependent variables; and through a multi-objective optimization, determining the first distance D1, the second distance D2 and the radius R with an optimization objective that the temperature rise ?Tj and the pressure drop ?Pf are simultaneously minimized.

Abstract: A package structure for a power semiconductor device is provided, including: a substrate; two or more semiconductor dies on the substrate, each of the semiconductor dies includes a first power switching pad, a second power switching pad and a gate; a gate control conductive trace, a first power switching contact and a second power switching contact are further arranged on the substrate, the gate control conductive trace is connected to each of the semiconductor dies via a bonding component, and the bonding component connecting a first semiconductor die to the gate control conductive trace is sandwiched between circuit lines formed by connecting the second power switching pads of the first semiconductor die and the neighboring second semiconductor die, to second power switching contact of the substrate.

Abstract: There is provided a power semiconductor device 1, comprising: a semiconductor substrate 2 comprising: a base layer 5 selectively provided at a first side of the semiconductor substrate, and wherein the base layer has a first conductivity type; a collector layer 3 provided at a second side of the semiconductor substrate, wherein the second side is opposite to the first side, and wherein the collector layer has the first conductivity type; and a drift layer 4 having a second conductivity type opposite to the first conductivity type, wherein the drift layer is arranged between the collector layer 3 and the base layer 5; an active cell 15 provided in the semiconductor substrate 2, wherein the active cell 15 comprises an emitter region 7 which has the second conductivity type, an active base region 5-i which is a part of the base layer 5, an active gate trench 9 comprising a gate insulator 11 and an active gate electrode 10 disposed therein, and wherein the active gate trench 9 is configured to extend from a surfa

Abstract: This disclosure relates to a virtual object control method. The method includes: displaying, by an electronic device, a first live streaming resource, the first live streaming resource including at least one selectable virtual object and at least one virtual object controlled by an anchor user; transmitting a control request when receiving a selection instruction for a target virtual object in the at least one selectable virtual object, the control request being for requesting to control the target virtual object; and controlling, in response to a control instruction for the target virtual object, the target virtual object to perform a target operation. With the foregoing method, viewer users can participate in live streaming when watching the live streaming, thereby improving the level of participation of the viewer users, and increasing interaction between the viewer users and the anchor user.

Abstract: We describe herein a high voltage semiconductor device comprising a power semiconductor device portion (100) and a temperature sensing device portion (185). The temperature sensing device portion comprises: an anode region (140), a cathode region (150), a body region (160) in which the anode region and the cathode region are formed. The temperature sensing device portion also comprises a semiconductor isolation region (165) in which the body region is formed, the semiconductor isolation region having an opposite conductivity type to the body region, the semiconductor isolation region being formed between the power semiconductor device portion and the temperature sensing device portion.

Abstract: An IGBT chip having a mixed gate structure includes a plurality of mixed gate units. Each of the mixed gate units includes a source region (3) and a gate region. The gate region includes a planar gate region (1) and a trench gate region (2), which are respectively disposed at both sides of the source region (3). A planar gate and a trench gate are compositely disposed on the same cell (16), thereby greatly improving chip density while retaining both trench gate's features of low on-state energy loss and high current density and planar gate's feature of wide safe operating area.

Abstract: We describe herein a high voltage semiconductor device comprising a power semiconductor device portion (100) and a temperature sensing device portion (185). The temperature sensing device portion comprises: an anode region (140), a cathode region (150), a body region (160) in which the anode region and the cathode region are formed. The temperature sensing device portion also comprises a semiconductor isolation region (165) in which the body region is formed, the semiconductor isolation region having an opposite conductivity type to the body region, the semiconductor isolation region being formed between the power semiconductor device portion and the temperature sensing device portion.

Abstract: An IGBT chip having a mixed gate structure includes a plurality of mixed gate units. Each of the mixed gate units includes a source region (3) and a gate region. The gate region includes a planar gate region (1) and a trench gate region (2), which are respectively disposed at both sides of the source region (3). A planar gate and a trench gate are compositely disposed on the same cell (16), thereby greatly improving chip density while retaining both trench gate's features of low on-state energy loss and high current density and planar gate's feature of wide safe operating area.