Patents by Inventor Chunlong Li
Chunlong Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10068803Abstract: A planarization process is disclosed. The method includes forming a trench in an area of a material layer which has a relatively high loading condition for sputtering. The method further includes sputtering the material layer to make the material layer flat.Type: GrantFiled: May 27, 2015Date of Patent: September 4, 2018Assignee: Institute of Microelectronics, Chinese Academy of SciencesInventors: Huilong Zhu, Jun Luo, Chunlong Li, Jian Deng, Chao Zhao
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Patent number: 9691624Abstract: Provided is a method for manufacturing a fin structure. The method may include forming an initial fin on a substrate, forming a dielectric layer on the substrate to cover the initial fin, planarizing the dielectric layer by sputtering, and further etching the dielectric layer back to expose a portion of the initial fin, wherein the exposed portion serves as a fin.Type: GrantFiled: December 14, 2012Date of Patent: June 27, 2017Assignee: Institute of Microelectronics, Chinese Academy of SciencesInventors: Huilong Zhu, Miao Xu, Jun Luo, Chunlong Li, Guilei Wang
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Publication number: 20160293695Abstract: The present disclosure provides a semiconductor device, comprising: a substrate having a first semiconductor material; a second semiconductor layer on the substrate; a third semiconductor layer on the second semiconductor layer and being a device formation region; an isolation structure on both sides of the third semiconductor layer and on the substrate; and an hollow cavity below the source and drain regions of the third semiconductor layer and between the isolation structure and the ends of the second semiconductor layer. Such a device structure of the present disclosure incorporate the respective advantages of the bulk silicon device and the SOI device, and has characteristics of lower cost, smaller leakage current, lower power consumption, fast speed, simple process and high integration level. Meanwhile, the floating body effect and the spontaneous heating effect are eliminated as compared with the SOI device.Type: ApplicationFiled: August 15, 2014Publication date: October 6, 2016Inventors: Jing Xu, Jiang Yan, Bangming Chen, Hongli Wang, Bo Tang, Zhaoyun Tang, Yefeng Xu, Chunlong Li, Mengmeng Yang
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Patent number: 9419112Abstract: A method for manufacturing a fin structure is provided. A method according to an embodiment may include: forming a patterned pattern transfer layer on a substrate; forming a first spacer on sidewalls of the pattern transfer layer; forming a second spacer on sidewalls of the first spacer; selectively removing the pattern transfer layer and the first spacer; and patterning the substrate with the second spacer as a mask, so as to form an initial fin.Type: GrantFiled: December 17, 2012Date of Patent: August 16, 2016Assignee: Institute of Microelectronics, Chinese Academy of SciencesInventors: Huilong Zhu, Jun Luo, Chunlong Li
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Patent number: 9419095Abstract: A method for manufacturing a dummy gate in a gate-last process and a dummy gate in a gate-last process are provided. The method includes: providing a semiconductor substrate; growing a gate oxide layer on the semiconductor substrate; depositing bottom-layer amorphous silicon on the gate oxide layer; depositing an ONO structured hard mask on the bottom-layer amorphous silicon; depositing top-layer amorphous silicon on the ONO structured hard mask; depositing a hard mask layer on the top-layer amorphous silicon; forming photoresist lines on the hard mask layer, and trimming the formed photoresist lines so that the trimmed photoresist lines a width less than or equal to 22 nm; and etching the hard mask layer, the top-layer amorphous silicon, the ONO structured hard mask and the bottom-layer amorphous silicon in accordance with the trimmed photoresist lines, and removing the photoresist lines, the hard mask layer and the top-layer amorphous silicon.Type: GrantFiled: December 12, 2012Date of Patent: August 16, 2016Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCESInventors: Chunlong Li, Junfeng Li, Jiang Yan, Chao Zhao
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Patent number: 9406549Abstract: A planarization process, the process including performing first sputtering on a material layer, with an area of the material layer which has a relatively low loading condition for sputtering shielded by a first shielding layer, removing the first shielding layer, and performing second sputtering on the material layer to planarize the material layer.Type: GrantFiled: December 20, 2012Date of Patent: August 2, 2016Assignee: Institute of Microelectronics, Chinese Academy of SciencesInventors: Huilong Zhu, Jun Luo, Chunlong Li, Jian Deng, Chao Zhao
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Patent number: 9331172Abstract: A method for manufacturing a dummy gate structure. The method may include: forming a dummy gate oxide layer and a dummy gate material layer on a semiconductor substrate sequentially; forming an ONO structure on the dummy gate material layer; forming a top amorphous silicon layer on the ONO structure; forming a patterned photoresist layer on the top amorphous silicon layer; etching the top amorphous silicon layer with the patterned photoresist layer as a mask, the etching being stopped on the ONO structure; etching the ONO structure with the patterned photoresist layer and a remaining portion of the top amorphous silicon layer as a mask, the etching being stopped on the dummy gate material layer; removing the patterned photoresist layer; and etching the dummy gate material layer, the etching being stopped at the dummy gate oxide layer to form a dummy gate structure.Type: GrantFiled: November 13, 2012Date of Patent: May 3, 2016Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCESInventors: Chunlong Li, Junfeng Li, Jiang Yan, Lingkuan Meng, Xiaobin He, Guanglu Chen, Chao Zhao
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Patent number: 9306003Abstract: A semiconductor device, including: a substrate having a first semiconductor material; a second semiconductor layer on the substrate; a third semiconductor layer on the second semiconductor layer and being a device formation region; an isolation structure on both sides of the third semiconductor layer and on the substrate; and an insulating layer below the source and drain regions of the third semiconductor layer and between the isolation structure and the ends of the second semiconductor layer.Type: GrantFiled: August 15, 2014Date of Patent: April 5, 2016Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCESInventors: Jing Xu, Jiang Yan, Bangming Chen, Hongli Wang, Bo Tang, Zhaoyun Tang, Yefeng Xu, Chunlong Li, Mengmeng Yang
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Publication number: 20160020274Abstract: A semiconductor device, including: a substrate having a first semiconductor material; a second semiconductor layer on the substrate; a third semiconductor layer on the second semiconductor layer and being a device formation region; an isolation structure on both sides of the third semiconductor layer and on the substrate; and an insulating layer below the source and drain regions of the third semiconductor layer and between the isolation structure and the ends of the second semiconductor layer.Type: ApplicationFiled: August 15, 2014Publication date: January 21, 2016Inventors: Jing Xu, Jiang Yan, Bangming Chen, Hongli Wang, Bo Tang, Zhaoyun Tang, Yefeng Xu, Chunlong Li, Mengmeng Yang
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Patent number: 9202890Abstract: A method for manufacturing a dummy gate in a gate-last process is provided. The method includes: providing a semiconductor substrate; growing a gate oxide layer on the semiconductor substrate; depositing bottom-layer amorphous silicon on the gate oxide layer; depositing an ONO structured hard mask on the bottom-layer amorphous silicon; depositing top-layer amorphous silicon on the ONO structured hard mask; depositing a hard mask layer on the top-layer amorphous silicon; forming photoresist lines having a width ranging from 32 nm to 45 nm on the hard mask layer; and etching the hard mask layer, the top-layer amorphous silicon, the ONO structured hard mask and the bottom-layer amorphous silicon in accordance with the photoresist lines, and removing the photoresist lines, the hard mask layer and the top-layer ?-Si. Correspondingly, a dummy gate in a gate-last process is also provided.Type: GrantFiled: December 12, 2012Date of Patent: December 1, 2015Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCESInventors: Chunlong Li, Junfeng Li, Jiang Yan, Chao Zhao
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Publication number: 20150325452Abstract: A planarization process, the process including performing first sputtering on a material layer, with an area of the material layer which has a relatively low loading condition for sputtering shielded by a first shielding layer, removing the first shielding layer, and performing second sputtering on the material layer to planarize the material layer.Type: ApplicationFiled: December 20, 2012Publication date: November 12, 2015Inventors: Huilong ZHU, Jun LUO, Chunlong LI, Jian DENG, Chao ZHAO
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Publication number: 20150303274Abstract: A method for manufacturing a fin structure is provided. A method according to an embodiment may include: forming a patterned pattern transfer layer on a substrate; forming a first spacer on sidewalls of the pattern transfer layer; forming a second spacer on sidewalls of the first spacer; selectively removing the pattern transfer layer and the first spacer; and patterning the substrate with the second spacer as a mask, so as to form an initial fin.Type: ApplicationFiled: December 17, 2012Publication date: October 22, 2015Inventors: Huilong ZHU, Jun LUO, Chunlong LI
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Publication number: 20150294879Abstract: Provided is a method for manufacturing a fin structure. The method may include forming an initial fin on a substrate, forming a dielectric layer on the substrate to cover the initial fin, planarizing the dielectric layer by sputtering, and further etching the dielectric layer back to expose a portion of the initial fin, wherein the exposed portion serves as a fin.Type: ApplicationFiled: December 14, 2012Publication date: October 15, 2015Inventors: Huilong Zhu, Miao Xu, Jun Luo, Chunlong Li, Guilei Wang
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Publication number: 20150262883Abstract: A planarization process is disclosed. The method includes forming a trench in an area of a material layer which has a relatively high loading condition for sputtering. The method further includes sputtering the material layer to make the material layer flat.Type: ApplicationFiled: May 27, 2015Publication date: September 17, 2015Inventors: Huilong Zhu, Jun Luo, Chunlong Li, Jian Deng, Chao Zhao
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Patent number: 9111863Abstract: A method for manufacturing a dummy gate in a gate-last process and a dummy gate in a gate-last process are provided. The method includes: providing a semiconductor substrate; growing a gate oxide layer on the semiconductor substrate; depositing bottom-layer amorphous silicon on the gate oxide layer; depositing an ONO structured hard mask on the bottom-layer amorphous silicon; depositing top-layer amorphous silicon on the ONO structured hard mask; depositing a hard mask layer on the top-layer amorphous silicon, and trimming the hard mask layer so that the trimmed hard mask layer has a width less than or equal to 22 nm; and etching the top-layer amorphous silicon, the ONO structured hard mask and the bottom-layer amorphous silicon in accordance with the trimmed hard mask layer, and removing the hard mask layer and the top-layer amorphous silicon.Type: GrantFiled: December 12, 2012Date of Patent: August 18, 2015Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCESInventors: Chunlong Li, Junfeng Li, Jiang Yan, Chao Zhao
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Publication number: 20150214332Abstract: A method for manufacturing a dummy gate structure. The method may include: forming a dummy gate oxide layer and a dummy gate material layer on a semiconductor substrate sequentially; forming an ONO structure on the dummy gate material layer; forming a top amorphous silicon layer on the ONO structure; forming a patterned photoresist layer on the top amorphous silicon layer; etching the top amorphous silicon layer with the patterned photoresist layer as a mask, the etching being stopped on the ONO structure; etching the ONO structure with the patterned photoresist layer and a remaining portion of the top amorphous silicon layer as a mask, the etching being stopped on the dummy gate material layer; removing the patterned photoresist layer; and etching the dummy gate material layer, the etching being stopped at the dummy gate oxide layer to form a dummy gate structure.Type: ApplicationFiled: November 13, 2012Publication date: July 30, 2015Inventors: Chunlong Li, Junfeng Li, Jiang Yan, Lingkuan Meng, Xiaobin He, Guanglu Chen, Chao Zhao
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Publication number: 20150035087Abstract: A method for manufacturing a dummy gate in a gate-last process and a dummy gate in a gate-last process are provided. The method includes: providing a semiconductor substrate; growing a gate oxide layer on the semiconductor substrate; depositing bottom-layer amorphous silicon on the gate oxide layer; depositing an ONO structured hard mask on the bottom-layer amorphous silicon; depositing top-layer amorphous silicon on the ONO structured hard mask; depositing a hard mask layer on the top-layer amorphous silicon; forming photoresist lines on the hard mask layer, and trimming the formed photoresist lines so that the trimmed photoresist lines a width less than or equal to 22 nm; and etching the hard mask layer, the top-layer amorphous silicon, the ONO structured hard mask and the bottom-layer amorphous silicon in accordance with the trimmed photoresist lines, and removing the photoresist lines, the hard mask layer and the top-layer amorphous silicon.Type: ApplicationFiled: December 12, 2012Publication date: February 5, 2015Inventors: Chunlong Li, Junfeng Li, Jiang Yan, Chao Zhao
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Patent number: 8926321Abstract: The present invention discloses a heating method for maintaining a stable thermal budget. By following the primary procedure with a virtual procedure in such a manner that the total duration of the whole heating process remains constant, it is beneficial to maintain a stable thermal budget and further to maintain a stable device performance.Type: GrantFiled: August 9, 2011Date of Patent: January 6, 2015Assignee: Institute of Microelectronics, Chinese Academy of SciencesInventor: Chunlong Li
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Publication number: 20140332958Abstract: A method for manufacturing a dummy gate in a gate-last process is provided. The method includes: providing a semiconductor substrate; growing a gate oxide layer on the semiconductor substrate; depositing bottom-layer amorphous silicon on the gate oxide layer; depositing an ONO structured hard mask on the bottom-layer amorphous silicon; depositing top-layer amorphous silicon on the ONO structured hard mask; depositing a hard mask layer on the top-layer amorphous silicon; forming photoresist lines having a width ranging from 32 nm to 45 nm on the hard mask layer; and etching the hard mask layer, the top-layer amorphous silicon, the ONO structured hard mask and the bottom-layer amorphous silicon in accordance with the photoresist lines, and removing the photoresist lines, the hard mask layer and the top-layer ?-Si. Correspondingly, a dummy gate in a gate-last process is also provided.Type: ApplicationFiled: December 12, 2012Publication date: November 13, 2014Inventors: Chunlong Li, Junfeng Li, Jiang Yan, Chao Zhao
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Publication number: 20140273426Abstract: A method for manufacturing a dummy gate in a gate-last process and a dummy gate in a gate-last process are provided. The method includes: providing a semiconductor substrate; growing a gate oxide layer on the semiconductor substrate; depositing bottom-layer amorphous silicon on the gate oxide layer; depositing an ONO structured hard mask on the bottom-layer amorphous silicon; depositing top-layer amorphous silicon on the ONO structured hard mask; depositing a hard mask layer on the top-layer amorphous silicon, and trimming the hard mask layer so that the trimmed hard mask layer has a width less than or equal to 22 nm; and etching the top-layer amorphous silicon, the ONO structured hard mask and the bottom-layer amorphous silicon in accordance with the trimmed hard mask layer, and removing the hard mask layer and the top-layer amorphous silicon.Type: ApplicationFiled: December 12, 2012Publication date: September 18, 2014Inventors: Chunlong Li, Junfeng Li, Jiang Yan, Chao Zhao