Abstract: A method and apparatus for accumulating and storing respective access counts of a plurality of word lines in a memory module are provided. The method may include: within a memory bank positioned in the memory module, providing a plurality of extraordinary storage cells coupled to the plurality of word lines; and utilizing the plurality of extraordinary storage cells to accumulate and store the respective access counts of the plurality of word lines, wherein multiple sets of extraordinary storage cells in the plurality of extraordinary storage cells correspond to the plurality of word lines, respectively.

Abstract: An one-time programmable memory cell includes: an upper electrode; an insulating layer beneath the upper electrode; and a lower electrode with electrical field enhancement structure beneath the insulating layer, wherein the electrical field enhancement structure has a least one tip portion. The one-time programmable memory cell also includes a shallow trench isolation region, disposed adjacent to the insulating layer and the lower electrode, wherein the electrical field enhancement structure is surrounded by the shallow trench isolation region and the upper electrode partially covers the shallow trench isolation region.

Abstract: A method and apparatus for accumulating and storing respective access counts of a plurality of word lines in a memory module are provided. The method may include: within a memory bank positioned in the memory module, providing a plurality of extraordinary storage cells coupled to the plurality of word lines; and utilizing the plurality of extraordinary storage cells to accumulate and store the respective access counts of the plurality of word lines, wherein multiple sets of extraordinary storage cells in the plurality of extraordinary storage cells correspond to the plurality of word lines, respectively.

Abstract: An one-time programmable memory cell includes: an upper electrode; an insulating layer beneath the upper electrode; and a lower electrode with electrical field enhancement structure beneath the insulating layer, wherein the electrical field enhancement structure has a least one tip portion. The one-time programmable memory cell also includes a shallow trench isolation region, disposed adjacent to the insulating layer and the lower electrode, wherein the electrical field enhancement structure is surrounded by the shallow trench isolation region and the upper electrode partially covers the shallow trench isolation region.

Abstract: A high speed test circuit receives a tester clock from a tester and it conducts a test on a circuit under test. The high speed test circuit generates a high frequency clock according to the tester clock, so it is capable of operating in two frequencies. The high speed test circuit tests the circuit under test according to the high frequency clock, and it performs a low speed operation according to a low frequency clock, which is for example the tester clock.

Abstract: A high speed test circuit receives a tester clock from a tester and it conducts a test on a circuit under test. The high speed test circuit generates a high frequency clock according to the tester clock, so it is capable of operating in two frequencies. The high speed test circuit tests the circuit under test according to the high frequency clock, and it performs a low speed operation according to a low frequency clock, which is for example the tester clock.

Abstract: A DLL with power-saving function includes a VCDL, a voltage control module, a capacitor, and a phase detector. The VCDL generates a delayed clock signal according to the voltage on the capacitor and a reference clock signal. The phase detector detects phase difference between the delayed clock signal and the reference clock signal and accordingly controls the voltage controller. The voltage controller sinks or sources current to the capacitor for adjusting the voltage on the capacitor. Further, the voltage controller can turn off its charge pump according to a turned-off signal and stops sinking or sourcing current for saving power.

Abstract: A DLL with power-saving function includes a VCDL, a voltage control module, a capacitor, and a phase detector. The VCDL generates a delayed clock signal according to the voltage on the capacitor and a reference clock signal. The phase detector detects phase difference between the delayed clock signal and the reference clock signal and accordingly controls the voltage controller. The voltage controller sinks or sources current to the capacitor for adjusting the voltage on the capacitor. Further, the voltage controller can turn off its charge pump according to a turned-off signal and stops sinking or sourcing current for saving power.

Abstract: Constant delay circuit includes signal input end, delay signal output end, RC delay circuit, and a comparator. The signal input end receives an input signal. The delay signal output end outputs the delay input signal, which the delay period is predetermined. The RC delay circuit is coupled to the signal input end for receiving the input signal and generating a voltage. The comparator includes a first input end, a second input end, and an output end. The first end of the comparator is coupled to the RC delay circuit for receiving the voltage. The second end of the comparator receives a reference voltage. The output end of the comparator is coupled to the delay signal output end of the long delay circuit. The comparator compares the reference voltage and the voltage, and accordingly generates a result as the delay signal.

Abstract: A signal sensing circuit and a semiconductor memory device using the same are provided. The signal sensing circuit comprises a sense amplifier, a kick transistor, a first control transistor, a second control transistor, a pre-charge circuit, and a recovery circuit. The kick transistor is used to pull up the operation voltage of the sense amplifier to improve the small signal sensing speed of the sense amplifier. After the signal is sensed, the recovery circuit will pull down the operation voltage of the sense amplifier to the standard level. In the present invention, the small signal sensing speed is greatly improved and the operation voltage of sense amplifier is kept away from the saturated level.

Abstract: A signal sensing circuit and a semiconductor memory device using the same are provided. The signal sensing circuit comprises a sense amplifier, a kick transistor, a first control transistor, a second control transistor, a pre-charge circuit, and a recovery circuit. The kick transistor is used to pull up the operation voltage of the sense amplifier to improve the small signal sensing speed of the sense amplifier. After the signal is sensed, the recovery circuit will pull down the operation voltage of the sense amplifier to the standard level. In the present invention, the small signal sensing speed is greatly improved and the operation voltage of sense amplifier is kept away from the saturated level.

Abstract: A shift down-level shifter used with a memory negative word line architecture prevents current flow between a positive bias voltage and a negative bias voltage when the input signal is at circuit ground. The output circuit of the shift down-level shifter comprises two transistors connecting a positive voltage and a negative voltage to the output terminal. A feed back circuit establishes a node voltage from which the output transistor coupling the negative voltage to the output terminal is controlled to be off when the input signal is at circuit ground and the output is a positive voltage, thus preventing current flow between the positive and negative bias voltages, which reduces power consumption.