Patents by Inventor Chuntian YU
Chuntian YU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10176854Abstract: A memory decoding system includes a memory decoding reference current module. The memory decoding reference current module includes: a first reference current unit connected to one end of a second reference bit line; a second reference current unit connected to one end of a first reference bit line; a third reference current unit connected to one end of a third reference bit line; a first reference NMOS transistor, a source of which is connected to the second reference bit line; a second reference NMOS transistor, a source of which is connected to a drain of the first reference NMOS transistor; and a gate of the first reference NMOS transistor and a gate of the second NMOS transistor are connected to a logic high level.Type: GrantFiled: January 2, 2018Date of Patent: January 8, 2019Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATIONInventors: Guangyan Luo, Hao Ni, Chuntian Yu, Xiaoyan Liu
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Publication number: 20180122437Abstract: A memory decoding system includes a memory decoding reference current module. The memory decoding reference current module includes: a first reference current unit connected to one end of a second reference bit line; a second reference current unit connected to one end of a first reference bit line; a third reference current unit connected to one end of a third reference bit line; a first reference NMOS transistor, a source of which is connected to the second reference bit line; a second reference NMOS transistor, a source of which is connected to a drain of the first reference NMOS transistor; and a gate of the first reference NMOS transistor and a gate of the second NMOS transistor are connected to a logic high level.Type: ApplicationFiled: January 2, 2018Publication date: May 3, 2018Inventors: GUANGYAN LUO, HAO NI, CHUNTIAN YU, XIAOYAN LIU
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Patent number: 9953689Abstract: A memory device may include the following elements: a first memory cell; a first word line for transmitting a first control signal to control an electrical connection in the first memory cell; a first bit line connected to the first memory cell; a first transistor, wherein a first terminal of the first transistor is connected to the first bit line; a second memory cell; a second word line for transmitting a second control signal to control an electrical connection in the second memory cell; a second bit line connected to the second memory cell; a second transistor, wherein a first terminal of the second transistor is connected to the second bit line; and a sense amplifier having a first input terminal connected to a second terminal of the first transistor and having a second input terminal connected to a second terminal of the second transistor.Type: GrantFiled: December 28, 2016Date of Patent: April 24, 2018Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATIONInventors: Yi Jin Kwon, Hao Ni, Hong Yu, Chuntian Yu
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Patent number: 9892769Abstract: The present disclosure provides control methods and control apparatus thereof and reference current modules of memory decoding systems. An exemplary control method of a memory decoding system comprising a decoder having at least a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor and a fourth NMOS transistor, a memory cell, and at least a first bit line and a second bit line, includes applying a first control signal, being at a logic low level during a first read operation stage of a read operation and at a logic high level during a second read operation stage after the first read operation stage of the read operation, to a gate of the first PMOS transistor; applying a second control signal to a gate of the second PMOS transistor; and applying a fourth control signal to a gate of the first NMOS transistor.Type: GrantFiled: August 29, 2016Date of Patent: February 13, 2018Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATIONInventors: Guangyan Luo, Hao Ni, Chuntian Yu, Xiaoyan Liu
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Publication number: 20170110167Abstract: A memory device may include the following elements: a first memory cell; a first word line for transmitting a first control signal to control an electrical connection in the first memory cell; a first bit line connected to the first memory cell; a first transistor, wherein a first terminal of the first transistor is connected to the first bit line; a second memory cell; a second word line for transmitting a second control signal to control an electrical connection in the second memory cell; a second bit line connected to the second memory cell; a second transistor, wherein a first terminal of the second transistor is connected to the second bit line; and a sense amplifier having a first input terminal connected to a second terminal of the first transistor and having a second input terminal connected to a second terminal of the second transistor.Type: ApplicationFiled: December 28, 2016Publication date: April 20, 2017Inventors: Yi Jin KWON, Hao NI, Hong YU, Chuntian YU
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Publication number: 20170062028Abstract: The present disclosure provides control methods and control apparatus thereof and reference current modules of memory decoding systems. An exemplary control method of a memory decoding system comprising a decoder having at least a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor and a fourth NMOS transistor, a memory cell, and at least a first bit line and a second bit line, includes applying a first control signal, being at a logic low level during a first read operation stage of a read operation and at a logic high level during a second read operation stage after the first read operation stage of the read operation, to a gate of the first PMOS transistor; applying a second control signal to a gate of the second PMOS transistor; and applying a fourth control signal to a gate of the first NMOS transistor.Type: ApplicationFiled: August 29, 2016Publication date: March 2, 2017Inventors: GUANGYAN LUO, HAO NI, CHUNTIAN YU, XIAOYAN LIU
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Patent number: 9570115Abstract: A memory device may include the following elements: a first memory cell; a first word line for transmitting a first control signal to control an electrical connection in the first memory cell; a first bit line connected to the first memory cell; a first transistor, wherein a first terminal of the first transistor is connected to the first bit line; a second memory cell; a second word line for transmitting a second control signal to control an electrical connection in the second memory cell; a second bit line connected to the second memory cell; a second transistor, wherein a first terminal of the second transistor is connected to the second bit line; and a sense amplifier having a first input terminal connected to a second terminal of the first transistor and having a second input terminal connected to a second terminal of the second transistor.Type: GrantFiled: November 17, 2015Date of Patent: February 14, 2017Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATIONInventors: Yi Jin Kwon, Hao Ni, Hong Yu, Chuntian Yu
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Publication number: 20160163366Abstract: A memory device may include the following elements: a first memory cell; a first word line for transmitting a first control signal to control an electrical connection in the first memory cell; a first bit line connected to the first memory cell; a first transistor, wherein a first terminal of the first transistor is connected to the first bit line; a second memory cell; a second word line for transmitting a second control signal to control an electrical connection in the second memory cell; a second bit line connected to the second memory cell; a second transistor, wherein a first terminal of the second transistor is connected to the second bit line; and a sense amplifier having a first input terminal connected to a second terminal of the first transistor and having a second input terminal connected to a second terminal of the second transistor.Type: ApplicationFiled: November 17, 2015Publication date: June 9, 2016Inventors: Yi Jin KWON, Hao NI, Hong YU, Chuntian YU
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Patent number: 8976546Abstract: A control integrated circuit for controlling a switch power supply, including: a voltage collecting module, configured to collect a feedback voltage based on an output voltage of the switch power supply; an error amplifying module, configured to compare the feedback voltage with a reference voltage and generate an error voltage; a time collecting module, configured to obtain a degaussing time signal based on the feedback voltage; and a constant voltage and current module, configured to collect a peak current feedback signal of a switch transistor, generate a control signal based on the error voltage, the degaussing time signal and the peak current feedback signal, wherein the control signal is for controlling an operating frequency and a duty ratio of the switch transistor, and control the switch transistor according to the control signal.Type: GrantFiled: July 30, 2012Date of Patent: March 10, 2015Assignees: Shenzhen BYD Auto R&D Company Limited, BYD Company LimitedInventors: Wenqing Wang, Xiaohua Yang, Chuntian Yu, Yuming Feng
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Publication number: 20130027985Abstract: A control integrated circuit for controlling a switch power supply, including: a voltage collecting module, configured to collect a feedback voltage based on an output voltage of the switch power supply; an error amplifying module, configured to compare the feedback voltage with a reference voltage and generate an error voltage; a time collecting module, configured to obtain a degaussing time signal based on the feedback voltage; and a constant voltage and current module, configured to collect a peak current feedback signal of a switch transistor, generate a control signal based on the error voltage, the degaussing time signal and the peak current feedback signal, wherein the control signal is for controlling an operating frequency and a duty ratio of the switch transistor, and control the switch transistor according to the control signal.Type: ApplicationFiled: July 30, 2012Publication date: January 31, 2013Inventors: Wenqing WANG, Xiaohua YANG, Chuntian YU, Yuming FENG