Abstract: A detonator for an explosive material is described. The detonator includes a semiconductor bridge, coupled with the explosive material, including thermal feedback mechanism is provided via one or more thermistors. An exemplary mechanism includes a semiconductor bridge with a polysilicon resistor and a pair of thermistors. The two thermistors are disposed to be substantially close to or sandwich the polysilicon resistor. When the temperature surrounding the polysilicon resistor is getting upwards, the temperature surrounding the thermistors is equally going up. When the temperature reaches a critical point, but below the threshold of the polysilicon resistor, the resistance of the thermistors drops suddenly or drastically, causing the current driving up the temperature of the polysilicon resistor to divert through the VOX temp resistors. Subsequently the current going through the polysilicon resistor is reduced, causing the temperature to drop downwards.

Abstract: The present application discloses a method and apparatus for generating an optimal H matrix. The method includes steps of: constructing an n*n fundamental matrix according to a preset constraint condition; performing a cyclic shift by taking each row vector of the fundamental matrix as a unit to generate (n?1) expansive matrixes; and generating a target H matrix according to the fundamental matrix and the expansive matrixes. Due to the implementation of the present application, an optimal H matrix is constructed by taking the thought of lowering the space complexity of an H matrix and reducing the hardware cost into consideration on the premise that a single-error-correcting and double-error-detecting function of a Hamming code is not affected; and a cyclic shift method is provided in combination with properties of the optimal H matrix, and a required target optimal H matrix may be formed by regularly expanding the constructed fundamental matrix.

Abstract: The disclosure relates to a method, computer program product or data processing system for performing graph-based static timing analysis, GBA, of an integrated circuit design having a set of timing paths. The method comprises identifying a subset of the set of timing paths and performing path-based analysis, PBA, of the subset of timing paths to determine at least one PBA timing parameter for each timing path of the subset of timing paths. The method further comprises determining at least one optimized GBA timing parameter for at least one timing path of the subset of timing paths by minimizing a function that is based on a difference between the at least one optimized GBA timing parameter and the at least one PBA timing parameter of the at least one timing path.

Abstract: The disclosure relates to a method, computer program product or data processing system for performing graph-based static timing analysis, GBA, of an integrated circuit design having a set of timing paths. The method comprises identifying a subset of the set of timing paths and performing path-based analysis, PBA, of the subset of timing paths to determine at least one PBA timing parameter for each timing path of the subset of timing paths. The method further comprises determining at least one optimized GBA timing parameter for at least one timing path of the subset of timing paths by minimizing a function that is based on a difference between the at least one optimized GBA timing parameter and the at least one PBA timing parameter of the at least one timing path.

Abstract: A computer implemented method for validating a clock tree includes estimating a first number of a multitude of first buffers disposed in the clock tree path, and selecting a first scaling coefficient in accordance with the first number. The computer implemented method further includes scaling a first delay associated with the multitude of first buffers in accordance with the selected first scaling coefficient, and generating a second multitude of second buffers disposed in the clock tree path defined by a second number greater than the first number.

Abstract: A method, system or computer usable program product for improving a circuit design having a set of endpoint circuits including identifying a subset of the set of endpoint circuits for further timing analysis based on graph based analysis (GBA) of the circuit design; performing path based analysis (PBA) of a set of endpoint circuit paths in the subset of endpoint circuits; and providing a timing margin between graph based analysis and path based analysis for each of the set of endpoint circuit paths for reducing pessimism in subsequent graph based analysis of the set of endpoint circuit paths.

Abstract: A computer implemented method for validating a clock tree includes estimating a first number of a multitude of first buffers disposed in the clock tree path, and selecting a first scaling coefficient in accordance with the first number. The computer implemented method further includes scaling a first delay associated with the multitude of first buffers in accordance with the selected first scaling coefficient, and generating a second multitude of second buffers disposed in the clock tree path defined by a second number greater than the first number.

Abstract: A method, system or computer usable program product for improving a circuit design having a set of endpoint circuits including identifying a subset of the set of endpoint circuits for further timing analysis based on graph based analysis (GBA) of the circuit design; performing path based analysis (PBA) of a set of endpoint circuit paths in the subset of endpoint circuits; and providing a timing margin between graph based analysis and path based analysis for each of the set of endpoint circuit paths for reducing pessimism in subsequent graph based analysis of the set of endpoint circuit paths.