Abstract: A wearable device includes a frame element and a dielectric substrate. The frame element includes a first metal element, a second metal element, and a third metal element. A first gap is provided between the first metal element and the second metal element. A second gap is provided between the second metal element and the third metal element. A third gap is provided between the third metal element and the first metal element. The dielectric substrate is surrounded by the first metal element, the second metal element, and the third metal element. A first antenna element is formed by the first metal element. A second antenna element is formed by the second metal element. A third antenna element is formed by the third metal element.

Abstract: A magnetic tunnel junction (MTJ) device includes two magnetic tunnel junction elements and a magnetic shielding layer. The two magnetic tunnel junction elements are arranged side by side. The magnetic shielding layer is disposed between the magnetic tunnel junction elements. A method of forming said magnetic tunnel junction (MTJ) device includes the following steps. An interlayer including a magnetic shielding layer is formed. The interlayer is etched to form recesses in the interlayer. The magnetic tunnel junction elements fill in the recesses. Or, a method of forming said magnetic tunnel junction (MTJ) device includes the following steps. A magnetic tunnel junction layer is formed. The magnetic tunnel junction layer is patterned to form magnetic tunnel junction elements. An interlayer including a magnetic shielding layer is formed between the magnetic tunnel junction elements.

Abstract: The present disclosure relates to a magneto-resistive random access memory (MRAM) cell having an extended upper electrode, and a method of formation. In some embodiments, the MRAM cell has a magnetic tunnel junction (MTJ) arranged over a conductive lower electrode. A conductive upper electrode is arranged over the magnetic tunnel junction. Below the conductive lower electrode is a first conductive via structure in a first dielectric layer. Below the conductive via structure is a discrete conductive jumper structure in a second dielectric layer. A dielectric body of a third dielectric material that is different from the first dielectric material and the second dielectric material extends vertical from the first dielectric layer at least partially into the second dielectric layer.

Abstract: A semiconductor device includes a substrate, a pair of semiconductor fins, a dummy fin structure, a gate structure, a plurality of source/drain structures, a crystalline hard mask layer, and an amorphous hard mask layer. The pair of semiconductor fins extend upwardly from the substrate. The dummy fin structure extends upwardly above the substrate and is laterally between the pair of semiconductor fins. The gate structure extends across the pair of semiconductor fins and the dummy fin structure. The source/drain structures are above the pair of semiconductor fins and on either side of the gate structure. The crystalline hard mask layer extends upwardly from the dummy fin and has an U-shaped cross section. The amorphous hard mask layer is in the first hard mask layer, wherein the amorphous hard mask layer having an U-shaped cross section conformal to the U-shaped cross section of the crystalline hard mask layer.

Abstract: A semiconductor device includes a substrate, a pair of semiconductor fins, a dummy fin structure, a gate structure, a plurality of source/drain structures, a crystalline hard mask layer, and an amorphous hard mask layer. The pair of semiconductor fins extend upwardly from the substrate. The dummy fin structure extends upwardly above the substrate and is laterally between the pair of semiconductor fins. The gate structure extends across the pair of semiconductor fins and the dummy fin structure. The source/drain structures are above the pair of semiconductor fins and on either side of the gate structure. The crystalline hard mask layer extends upwardly from the dummy fin and has an U-shaped cross section. The amorphous hard mask layer is in the first hard mask layer, wherein the amorphous hard mask layer having an U-shaped cross section conformal to the U-shaped cross section of the crystalline hard mask layer.

Abstract: A fundus camera includes an objective lens, an illumination device, an imaging lens group and an image sensor. The illumination device has a light emitting position and includes a plurality of light emitting modules and a driving element. Each light emitting module generates a corresponding illumination light, and the optical characteristics of the illumination lights are different from each other. The driving element drives one of the light emitting modules to the light emitting position of the illumination device to output an illumination light with required optical characteristics and irradiate it to a fundus through the objective lens. The imaging light reflected by the fundus passes through the objective lens and the imaging lens group to form an image on the image sensor so as to generate a fundus image. The abovementioned fundus camera has a compact structure and can switch the illumination light sources in a short time to obtain fundus images with different optical characteristics.

Abstract: A bonding structure of an electrical contact, a bonding method of the electrical contact and a battery module are provided. The bonding structure of the electrical contact includes an electroconductive part and an electrode sheet welded to the electroconductive part. The electrode sheet is a first metal material, and the electroconductive part is a second metal material. A welding track is formed on an interface formed by combining the electrode sheet with the electroconductive part. The welding track is a mixture of the first metal material and the second metal material. The welding track substantially has no overlap. In addition, the welding track includes a moving path, and a lateral path of performing a wobble movement or an oscillation movement on lateral sides of the moving path.

Abstract: A method for fabricating a semiconductor integrated circuit (IC) having a SONOS memory device and a logic/analog device requiring different gate oxide layers comprises steps as follows: A substrate having a high voltage region, a memory region and a logic/analog is firstly provided. Next, a first gate oxide layer is formed on the high voltage region, the memory region and the logic/analog. The first gate oxide layer is then patterned to expose the logic/analog region and to define a first channel area and a second channel area respectively on the memory region and the high voltage region. Subsequently, a silicon oxide-silicon nitride-silicon oxide (ONO) structure is formed on the first channel area. A second gate oxide layer is then formed on the logic/analog and patterned to define a third channel area.

Abstract: A method for fabricating a semiconductor integrated circuit (IC) having a SONOS memory device and a logic/analog device requiring different gate oxide layers comprises steps as follows: A substrate having a high voltage region, a memory region and a logic/analog is firstly provided. Next, a first gate oxide layer is formed on the high voltage region, the memory region and the logic/analog. The first gate oxide layer is then patterned to expose the logic/analog region and to define a first channel area and a second channel area respectively on the memory region and the high voltage region. Subsequently, a silicon oxide-silicon nitride-silicon oxide (ONO) structure is formed on the first channel area. A second gate oxide layer is then formed on the logic/analog and patterned to define a third channel area.

Abstract: A wafer processing chamber is provided, including a first processing gas supply unit and a second processing gas supply unit. The first processing gas supply unit is configured for supplying a first processing gas to form a first processing zone in the wafer processing chamber. The second processing gas supply unit is configured for supplying a second processing gas into the wafer processing chamber to form a second processing zone in the wafer processing chamber. In the wafer processing chamber, the first processing zone and the second processing zone are virtually separated from each other, such that a process wafer in the first processing zone may be performed a different process from another process wafer in the second processing zone at the same time. Further, a heat treatment apparatus and a method for processing wafers also provide herein.

Abstract: A method for checking mask design of an integrated circuit, wherein the integrated circuit includes a plurality of functional elements arranged at different positions, the method includes generating implant layer data of each functional element of the integrated circuit according to characteristics of each functional element; generating mask design data of the integrated circuit according to circuit design of the integrated circuit; generating a block diagram of the integrated circuit according to the mask design data; determining a corresponding position of the functional element in the block diagram according to the implant layer data; and comparing the implant layer data of the functional element with the mask design data at the corresponding position.

Abstract: The present invention discloses a method for node addition and removal of a circuit. The steps of the method include: (a) providing a circuit with a plurality of nodes; (b) selecting a target node for computing mandatory assignments (MAs) of stuck-at 0 and stuck-at 1 fault tests on the target node, respectively, by a processing unit; (c) finding an added substitute node by utilizing the MAs of stuck-at 0 and stuck-at 1 fault tests of the target node by the processing unit; and (d) replacing the target node by using the added substitute node closest to primary inputs; and (e) the steps (b)˜(d) are repeated for removing the replaceable nodes and simplifying the circuit.

Abstract: The present invention discloses a method for fast detection of node mergers and simplification of a circuit. The steps of the method include: (a) a circuit with a large amount of nodes is provided; (b) a target node is selected for computing mandatory assignments (MAs) of the stuck-at 0 and stuck-at 1 fault tests on the target node respectively by a computer; (c) the MAs of the stuck-at 0 and stuck-at 1 fault tests of the target node are utilized to find substitute nodes; (d) the substitute node that is closest to primary inputs is used to replace the target node; and (e) the steps (b)˜(d) are repeated for removing the replaceable nodes and simplifying the circuit.

Abstract: An apparatus for clamping both large and small disks is provided, including a disk tray inside a base, an upper case and two clamping mechanisms above the disk tray and the base. Each clamping mechanism includes a slider and a gripper structure. The gripper structure further includes a first gripper, a second gripper, and a resilient element located between the first and the second grippers. The second gripper includes a first belt-ring and a second belt-ring. When the disk is loaded, under the force of the resilient element, the first belt-ring and the second belt-ring hold the disk onto the disk tray firmly. When the first gripper moves to a specific position of the groove on the upper case, the first gripper causes the second gripper to rotate so that the resilient element stops to exert the force. Hence, the first belt-ring and the second belt-ring rotate upwards so as to complete the loading process.

Abstract: This invention proposes a new restructuring technique, Rewiring Using IRredundancy Removal and Addition (IRRA) used in the synthesis and optimization of logic designs. This method successfully removes any desired target wire by constructing a corresponding rectification network which exactly corrects the error of the circuit caused by the removal of the target wire. The rectification network can be further simplified to achieve excellent area optimization.

Abstract: A method for preparing a doped polysilicon conductor according to this aspect of the present invention comprises the steps of (a) placing a substrate in a reaction chamber, (b) performing a deposition process to form a polysilicon layer on the substrate, (c) performing a grain growth process to form a plurality of polysilicon grains on the polysilicon layer, and (d) performing a dopant diffusion process to diffuse conductive dopants into the polysilicon layer via the polysilicon grains to form the doped polysilicon conductor.

Abstract: An apparatus for clamping both large and small disks is provided, including a disk tray inside a base, an upper case and two clamping mechanisms above the disk tray and the base. Each clamping mechanism includes a slider and a gripper structure. The gripper structure further includes a first gripper, a second gripper, and a resilient element located between the first and the second grippers. The second gripper includes a first belt-ring and a second belt-ring. When the disk is loaded, under the force of the resilient element, the first belt-ring and the second belt-ring hold the disk onto the disk tray firmly. When the first gripper moves to a specific position of the groove on the upper case, the first gripper causes the second gripper to rotate so that the resilient element stops to exert the force. Hence, the first belt-ring and the second belt-ring rotate upwards so as to complete the loading process.

Abstract: A reversible sequential apparatus comprises a first logic gate and a second logic gate. The first logic gate includes first, second and third input terminals and first, second and third output terminals. The second logic gate includes first and second input lines and first and second output lines. The first input terminal for carrying a clock signal is coupled to the first output terminal and the second input terminal for carrying an input signal is coupled to the second output terminal. When the first input terminal and the second input terminal are simultaneously set to a first state, the level of the third output terminal is inverse to the level of the third input terminal; otherwise, the level of the third output terminal is identical to the level of the third input terminal. The third output terminal, second input line and second output line are coupled to each other.

Abstract: A reversible sequential apparatus comprises a first logic gate and a second logic gate. The first logic gate includes first, second and third input terminals and first, second and third output terminals. The second logic gate includes first and second input lines and first and second output lines. The first input terminal for carrying a clock signal is coupled to the first output terminal and the second input terminal for carrying an input signal is coupled to the second output terminal. When the first input terminal and the second input terminal are simultaneously set to a first state, the level of the third output terminal is inverse to the level of the third input terminal; otherwise, the level of the third output terminal is identical to the level of the third input terminal. The third output terminal, second input line and second output line are coupled to each other.

Abstract: A reversible sequential element comprises a first logic gate and a second logic gate. The first logic gate includes a first input terminal, a second input terminal, a third input terminal, a first output terminal coupled to the first input terminal, a second output terminal and a third output terminal. The second logic gate includes a first input line, a second input line, a first output line and a second output line. When the first input terminal is set to a first state, the second input terminal is coupled to the third output terminal and the third input terminal is coupled to the second output terminal; otherwise, the second input terminal is coupled to the second output terminal and the third input terminal is coupled to the third output terminal. The third output terminal, second input line and second output line are coupled to each other. The input signal carried on the first input line is set as 0 so that the second output line and the first output line have the same output.