Abstract: A processor configured to store prediction information that is obtained from a call instruction that is fetched in a RAS fetch, acquire the prediction information that is used in a return instruction from the RAS fetch, delete the prediction information, store the prediction information in a RAS complete after completion of execution of the call instruction, and delete the prediction information from the RAS complete after completion of execution of the return instruction, and specify a first entry that is the closest to a top of the queue among the entries in which the branch instruction on which the branch prediction error is detected is re-executed, store and delete the prediction information in and from the RAS fetch according to the call instruction and the return instruction that are stored in entries closer to the top than the first entry is, and cause the first entry to be re-executes.