Abstract: The present invention relates to a range of halide organic salts and their use in a cathode of an electrical cell and in batteries. Elemental halides have attracted intense interest as promising electrodes for energy storage. However, they suffer from a number of inherent physicochemical drawbacks, including the volatility of iodine, the corrosiveness of liquid bromine. The salts of the present invention may serve as a cathode matched with a zinc anode avoiding these issues.

Abstract: The present invention relates to a pyrazolo[1,5-a]pyridine derivative, a preparation method therefor, and a composition and a use thereof. Specifically, the present invention relates to the compound of formula (I) and the use thereof for the treatment and/or prevention of wild type, gene-fusion type (including but not limited to KIF5B, CCDC6 and NCOA4) and mutant type (including but not limited to V804, G810 and M918) RET kinases-related diseases, including diseases or conditions mediated by RET kinase.

Abstract: The application discloses a device and a method for picking up top k values from N values.

Abstract: A method for catalytic cracking of naphtha is provided. Naphtha is catalytically cracked under the action of a catalyst. The catalyst includes aluminosilicate, alkali metal oxide, alkaline earth metal oxide, TiO2, iron oxide, vanadium oxide and nickel oxide. On the other hand, a rapid separation component is arranged in a disengager of a catalytic cracking reaction device, so that a transport disengaging height is greatly reduced without changing a gas flow and a diameter of the disengager. In addition, the separation efficiency of oil gas and the catalyst is improved.

Abstract: A method for querying in a candidate vector set candidate vectors similar to object vectors is disclosed, wherein the candidate vector set comprises a plurality of candidate vectors each being quantized as having a central vector portion and a residual vector portion, and the candidate vector set comprises a plurality of candidate vector subsets, the method comprising: acquiring a set of object vectors; querying, for each object vector of the set of object vectors, a first number of candidate vector subsets that are closest to the object vector; generating and storing a plurality of common calculation results based on a set of central vector portions and a set of residual vector portions of candidate vectors of the first number of candidate vector subsets; generating and storing pre-calculation results based on the set of object vectors and the set of residual vector portion; and determining, for each object vector of the set of object vectors, a second number of candidate vectors that are similar to the obje

Abstract: Disclosed is an alkane dehydrogenation circulating device, including a reaction device and a regeneration device. The reaction device includes a reactor and a reaction disengager, the reaction disengager is communicated with the reactor, and the reactor is provided with a catalyst distributor through which a catalyst is sprayed into the reactor along a direction from the peripheral wall of the reactor to the central axis of the reactor; the regeneration device includes a regenerator accommodating the catalyst and a regeneration disengager located above the regenerator.

Abstract: A method for catalytic cracking of naphtha is provided. Naphtha is catalytically cracked under the action of a catalyst. The catalyst includes aluminosilicate, alkali metal oxide, alkaline earth metal oxide, TiO2, iron oxide, vanadium oxide and nickel oxide. On the other hand, a rapid separation component is arranged in a disengager of a catalytic cracking reaction device, so that a transport disengaging height is greatly reduced without changing a gas flow and a diameter of the disengager. In addition, the separation efficiency of oil gas and the catalyst is improved.

Abstract: The application discloses a memory controller coupled to a memory module for controlling access to the memory module. The memory controller comprises: a registering clock driver coupled to the memory module for providing a data access command to the memory module so as to control access to the memory module; and a data buffer coupled between the registering clock driver and the memory module for exchanging data between the memory module and the registering clock driver under the control of the registering clock driver; wherein the registering clock driver comprises a computing unit for computing the data received via the data buffer from the memory module and providing a computing result to the memory module via the data buffer.

Abstract: The present application discloses a computing device and a neural network processor including the computing device. The computing device includes one or more columns of computing units arranged in an array, wherein at least one computing unit in each column comprises: an arithmetic parameter memory for storing one or more arithmetic parameters; an arithmetic logical unit (ALU) for receiving input data and performing computation on the input data using the one or more arithmetic parameters stored in the arithmetic parameter memory; and an address controller for providing an address control signal to the arithmetic parameter memory to control the storage and output of the one or more arithmetic parameters.

Abstract: The application discloses a memory controller coupled to a memory module for controlling access to the memory module, wherein the memory module comprises one or more memory groups each having a plurality of memory blocks, and the memory controller comprising: a registering clock driver coupled to the memory module for providing to the memory module a data access command so as to control access to the memory module; one or more data buffers coupled to the registering clock driver, and each data buffer coupled to a memory group via a memory group data interface; wherein at least one of the memory group data interfaces comprises a plurality of data buses each coupled to one or more memory blocks of the memory group that the memory group data interface coupled to, such that the memory group can exchange data with the data buffer via the plurality of data buses under the control of the registering clock driver.

Abstract: The present application discloses a computing device and a neural network processor including the computing device. The computing device includes one or more columns of computing units arranged in an array, wherein at least one computing unit in each column comprises: an arithmetic parameter memory for storing one or more arithmetic parameters; an arithmetic logical unit (ALU) for receiving input data and performing computation on the input data using the one or more arithmetic parameters stored in the arithmetic parameter memory; and an address controller for providing an address control signal to the arithmetic parameter memory to control the storage and output of the one or more arithmetic parameters.

Abstract: The application discloses a memory controller coupled to a memory module for controlling access to the memory module, wherein the memory module comprises one or more memory groups each having a plurality of memory blocks, and the memory controller comprising: a registering clock driver coupled to the memory module for providing to the memory module a data access command so as to control access to the memory module; one or more data buffers coupled to the registering clock driver, and each data buffer coupled to a memory group via a memory group data interface; wherein at least one of the memory group data interfaces comprises a plurality of data buses each coupled to one or more memory blocks of the memory group that the memory group data interface coupled to, such that the memory group can exchange data with the data buffer via the plurality of data buses under the control of the registering clock driver.

Abstract: The application discloses a memory controller coupled to a memory module for controlling access to the memory module. The memory controller comprises: a registering clock driver coupled to the memory module for providing a data access command to the memory module so as to control access to the memory module; and a data buffer coupled between the registering clock driver and the memory module for exchanging data between the memory module and the registering clock driver under the control of the registering clock driver; wherein the registering clock driver comprises a computing unit for computing the data received via the data buffer from the memory module and providing a computing result to the memory module via the data buffer.

Abstract: A reaction-regeneration device for catalytic dehydrogenation or/and catalytic cracking of alkanes comprises a reaction device and a regeneration device. The reaction device comprises a reactor and a disengager, and the disengager is located at an upper part of the reactor. The reactor comprises a tapering section, and diameters of cross sections of the tapering section gradually decrease from bottom to top. Secondary conversion of alkenes caused by back-mixing is reduced, and thus the yield and selectivity to alkenes are increased.

Abstract: A reaction-regeneration device for catalytic dehydrogenation or/and catalytic cracking of alkanes comprises a reaction device and a regeneration device. The reaction device comprises a reactor and a disengager, and the disengager is located at an upper part of the reactor. The reactor comprises a tapering section, and diameters of cross sections of the tapering section gradually decrease from bottom to top. Secondary conversion of alkenes caused by back-mixing is reduced, and thus the yield and selectivity to alkenes are increased.

Abstract: A reaction-regeneration device for catalytic dehydrogenation or/and catalytic cracking of alkanes comprises a reaction device and a regeneration device. The reaction device comprises a reactor and a disengager, and the disengager is located at an upper part of the reactor. The reactor comprises a tapering section, and diameters of cross sections of the tapering section gradually decrease from bottom to top. Secondary conversion of alkenes caused by back-mixing is reduced, and thus the yield and selectivity to alkenes are increased.

Abstract: A reaction-regeneration device for catalytic dehydrogenation or/and catalytic cracking of alkanes comprises a reaction device and a regeneration device. The reaction device comprises a reactor and a disengager, and the disengager is located at an upper part of the reactor. The reactor comprises a tapering section, and diameters of cross sections of the tapering section gradually decrease from bottom to top. Secondary conversion of alkenes caused by back-mixing is reduced, and thus the yield and selectivity to alkenes are increased.

Abstract: A voltage and timing calibration method used in a memory system. A memory controller adjusts timing and voltages of the controller and voltages of a memory buffer according to data returned by the buffer based on timing and voltages at a memory controller side of the buffer, to calibrate timing and voltages between the controller and controller side. According to data read by the buffer from a memory chip unit on the basis of timing and voltages at a memory chip side of the buffer, the controller adjusts the timing and voltage at the chip side and the voltage of the chip unit; or the buffer adjusts the timing and voltage at the chip side and the voltage of the chip unit, to calibrate the timing and voltage between the chip side and chip unit. Therefore, hardware resources of the buffer can be saved and the circuit can be simplified.

Abstract: A device requiring address allocation, a device system, and an address allocation method. A control device in the device system transmits currently allocated address information and a contention start signal to each device requiring address allocation in the device system through a bus, and the devices requiring address allocation with address allocation flag information being that no address information is allocated output an address contention signal. When outputting the address contention signal, each device requiring address allocation determines whether the currently allocated address information is available according to whether the other devices requiring address allocation with address allocation flag information being that no address information is allocated already output address contention signals.

Abstract: A device requiring address allocation, a device system, and an address allocation method. A control device in the device system transmits currently allocated address information and a contention start signal to each device requiring address allocation in the device system through a bus, and the devices requiring address allocation with address allocation flag information being that no address information is allocated output an address contention signal. When outputting the address contention signal, each device requiring address allocation determines whether the currently allocated address information is available according to whether the other devices requiring address allocation with address allocation flag information being that no address information is allocated already output address contention signals.