Patents by Inventor Chunying Han

Chunying Han has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Overlay alignment mark and method for measuring overlay error
    Patent number: 11934109
    Abstract: An overlay alignment mark located in a patterned wafer and a method for measuring overlay error are provided, the patterned wafer having a lower-layer pattern in a first layer thereof and an upper-layer pattern in a second layer thereof above the first layer, the overlay alignment mark comprising: a first pattern, which is a portion of the lower-layer pattern and comprises a pair of solid features formed in the first layer; and a second pattern, which is a portion of the upper-layer pattern and comprises two pairs of hollowed features formed in the second layer, with two imaginary lines connecting between geometric centers of respective pairs in the two pairs of hollowed features extending in two mutually orthogonal directions, respectively; an orthographic projection of the pair of solid features on the wafer at least partially overlaps with an orthographic projection of a respective pair of hollowed features on the wafer.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: March 19, 2024
    Assignee: Zhongke Jingyuan Electron Limited, Beijing (CN)
    Inventors: Weimin Ma, Chunying Han, Chengcheng Liu, Shouyan Huang
  • Overlay Alignment Mark and Method for Measuring Overlay Error
    Publication number: 20210382402
    Abstract: An overlay alignment mark located in a patterned wafer and a method for measuring overlay error are provided, the patterned wafer having a lower-layer pattern in a first layer thereof and an upper-layer pattern in a second layer thereof above the first layer, the overlay alignment mark comprising: a first pattern, which is a portion of the lower-layer pattern and comprises a pair of solid features formed in the first layer; and a second pattern, which is a portion of the upper-layer pattern and comprises two pairs of hollowed features formed in the second layer, with two imaginary lines connecting between geometric centers of respective pairs in the two pairs of hollowed features extending in two mutually orthogonal directions, respectively; an orthographic projection of the pair of solid features on the wafer at least partially overlaps with an orthographic projection of a respective pair of hollowed features on the wafer.
    Type: Application
    Filed: May 10, 2021
    Publication date: December 9, 2021
    Inventors: Weimin Ma, Chunying Han, Chengcheng Liu, Shouyan Huang
  • OVERLAY ALIGNMENT MARK, METHOD FOR MEASURING OVERLAY ERROR, AND METHOD FOR OVERLAY ALIGNMENT
    Publication number: 20210382401
    Abstract: An overlay alignment mark, a method for measuring overlay error, and a method for overlay alignment are provided in the embodiments of the present disclosure.
    Type: Application
    Filed: May 27, 2021
    Publication date: December 9, 2021
    Inventors: Chengcheng LIU, Chunying Han, Weimin MA, Shouyan Huang