Abstract: A rectilinear-block placement method includes disposing a first sub-block of each flexible block on a layout area of a chip canvas according to a reference position, generating an edge-depth map relative to first sub-blocks of flexible blocks on the layout area, predicting positions of second sub-blocks of the flexible blocks with depth values on the edge-depth map by a machine learning model, and positioning the second sub-blocks on the layout area according to the predicted positions of the second sub-blocks of the flexible blocks.

Abstract: A method forming a semiconductor package device includes: providing a substrate; forming a flip chip die on a first side on the substrate; and forming a molding compound on the first side of the substrate. The molding compound covers the flip chip die. The method further includes forming a heat sink on the molding compound; and forming a taping layer on a second side of the substrate, wherein the second side is opposite from the first side in a vertical direction. After forming the taping layer, the method further includes performing a pre-cut process and an etching process on the heat sink; and removing the taping layer.

Abstract: A semiconductor device includes a gate structure on a substrate, a first spacer on a sidewall of the gate structure, a second spacer on a sidewall of the first spacer, a third spacer on a sidewall of the second spacer, and first and second stacks of an epitaxial layer and a cap layer respectively disposed at first and second sides of the gate structure. Preferably, a part of the second spacer comprises an I-shape, the cap layer includes a planar top surface and an inclined sidewall, the cap layer contacts the second spacer and the third spacer directly, and the cap layer includes a vertical sidewall connected to the inclined sidewall.

Abstract: The application discloses a method and a system for shaping flexible blocks on a chip canvas in an integrated circuit design. An input is received describing geometric features of flexible blocks. A set of flexible blocks are generated based on the input. Obtained block areas of the set of flexible blocks are computed. Whether the set of flexible blocks are legal is determined based on determining whether area differences between the obtained block areas and a plurality of required areas for the set of flexible blocks meet a requirement. The set of flexible blocks are updated until the set of flexible blocks are all legal.

Abstract: The instant disclosure provides a gate device and an umbrella sharing system which utilizes the gate device. The gate device includes a base, an actuator, a pair of gate plates, and an identification sensor. The actuator is disposed on a top surface of the base and includes a latch extending downward through the base. The pair of gate plates are disposed on a bottom surface of the base, and each of the gate plates includes a guiding structure and a locking structure. A waiting zone for receiving an umbrella is defined between the two guiding structures. The latch of the actuator is driven to engage with the locking structures to limit the movement of the gate plates. The identification sensor is above the waiting zone and disposed on the base and is configured to identify the identity of an umbrella which enters the waiting zone.

Abstract: A method forming a semiconductor package device includes: providing a substrate; forming a flip chip die on a first side on the substrate; and forming a molding compound on the first side of the substrate. The molding compound covers the flip chip die. The method further includes forming a heat sink on the molding compound; and forming a taping layer on a second side of the substrate, wherein the second side is opposite from the first side in a vertical direction. After forming the taping layer, the method further includes performing a pre-cut process and an etching process on the heat sink; and removing the taping layer.

Abstract: The present disclosure relates to a transistor device having a channel region comprising a sandwich film stack with a plurality of different layers that improve device performance, and an associated apparatus. In some embodiments, the transistor device has a source region and a drain region disposed within a semiconductor substrate. A sandwich film stack is laterally positioned between the source region and the drain region. The sandwich film stack has a lower layer, a middle layer of a carbon doped semiconductor material disposed over the lower layer, and an upper layer disposed over the middle layer. A gate structure is disposed over the sandwich film stack. The gate structure is configured to control a flow of charge carriers in a channel region located between the source region and the drain region.

Abstract: The present disclosure relates to a transistor device having a channel region comprising a sandwich film stack with a plurality of different layers that improve device performance, and an associated apparatus. In some embodiments, the transistor device has a source region and a drain region disposed within a semiconductor substrate. A sandwich film stack is laterally positioned between the source region and the drain region. The sandwich film stack has a lower layer, a middle layer of a carbon doped semiconductor material disposed over the lower layer, and an upper layer disposed over the middle layer. A gate structure is disposed over the sandwich film stack. The gate structure is configured to control a flow of charge carriers in a channel region located between the source region and the drain region.

Abstract: The present disclosure relates to a method of forming a transistor device having a channel region comprising a sandwich film stack with a plurality of different layers that improve device performance, and an associated apparatus. In some embodiments, the method is performed by selectively etching a semiconductor substrate to form a recess along a top surface of the semiconductor substrate. A sandwich film stack having a plurality of nested layers is formed within the recess. At least two of the nested layers include different materials that improve different aspects of the performance of the transistor device. A gate structure is formed over the sandwich film stack. The gate structure controls the flow of charge carriers in a channel region having the sandwich film stack, which is laterally positioned between a source region and a drain region disposed within the semiconductor substrate.

Abstract: A method includes forming a dummy gate stack over a semiconductor substrate, removing the dummy gate stack to form a recess, and implanting a portion of the semiconductor substrate through the recess. During the implantation, an amorphous region is formed from the portion of the semiconductor substrate. The method further includes forming a strained capping layer, wherein the strained capping layer extends into the recess. An annealing is performed on the amorphous region to re-crystallize the amorphous region. The strained capping layer is then removed.

Abstract: The present disclosure relates to a method of forming a transistor device having a channel region comprising a sandwich film stack with a plurality of different layers that improve device performance, and an associated apparatus. In some embodiments, the method is performed by selectively etching a semiconductor substrate to form a recess along a top surface of the semiconductor substrate. A sandwich film stack having a plurality of nested layers is formed within the recess. At least two of the nested layers include different materials that improve different aspects of the performance of the transistor device. A gate structure is formed over the sandwich film stack. The gate structure controls the flow of charge carriers in a channel region having the sandwich film stack, which is laterally positioned between a source region and a drain region disposed within the semiconductor substrate.

Abstract: A method includes forming a dummy gate stack over a semiconductor substrate, removing the dummy gate stack to form a recess, and implanting a portion of the semiconductor substrate through the recess. During the implantation, an amorphous region is formed from the portion of the semiconductor substrate. The method further includes forming a strained capping layer, wherein the strained capping layer extends into the recess. An annealing is performed on the amorphous region to re-crystallize the amorphous region. The strained capping layer is then removed.

Abstract: A fatigue test apparatus for thin workpiece includes a supporting module, a driving mechanism, a first connecting module, a second connecting module, a first holding post, a second holding post and a computer system. The first and second connecting modules are respectively fixed to two sides of the supporting module. Ends of the first holding post and the second holding post are fixed to the first and second connecting modules. The computer system electronically connects with and controls the driving mechanism. The first holding post and the second holding post are drive to rotate by the driving mechanism.

Abstract: A resistance testing device detects resistances between testing points of an electronic element. The resistance testing device includes controls accepting input of data to the resistance testing device, a relay module, a multimeter, testing probes electrically connected to the relay module, a testing platform including a base and a probe mounting board, a driving assembly mounted on the base and moving the probe mounting board relative to the electronic device, a display, and a central processing assembly mounted within the base. The relay module controls the testing probes and implements the multimeter to detect resistances between the testing points. The base seats the electronic element, the probe mounting board fixes the testing probes, and the probe mounting board is adjustably mounted above the base. The central processing assembly includes a central processing unit. The central processing unit is respectively and electronically connected to the controls, driving assembly, display and the relay module.

Abstract: A fatigue test apparatus for thin workpiece includes a supporting module, a driving mechanism, a first connecting module, a second connecting module, a first holding post, a second holding post and a computer system. The first and second connecting modules are respectively fixed to two sides of the supporting module. Ends of the first holding post and the second holding post are fixed to the first and second connecting modules. The computer system electronically connects with and controls the driving mechanism. The first holding post and the second holding post are drive to rotate by the driving mechanism.

Abstract: A test apparatus for testing a separation force between a housing (92) and a subsidiary element (94) of a portable electronic device (100). The housing defines a plurality of through holes. The subsidiary element is attached to the housing, and covers the through holes. The test apparatus includes: a positioning apparatus (50), a push mechanism (60) and a test machine (70). The positioning apparatus positions the housing with the subsidiary element therein. The push mechanism includes a support board (62) and a plurality of rods (64). The rods are mounted in the support board. The rods pass through the through holes and resisting the subsidiary element. The test machine provides a driven force to press the support board to separate the subsidiary element from the housing.

Abstract: A test apparatus for testing a separation force between a housing (92) and a subsidiary element (94) of a portable electronic device (100). The housing defines a plurality of through holes. The subsidiary element is attached to the housing, and covers the through holes. The test apparatus includes: a positioning apparatus (50), a push mechanism (60) and a test machine (70). The positioning apparatus positions the housing with the subsidiary element therein. The push mechanism includes a support board (62) and a plurality of rods (64). The rods are mounted in the support board. The rods pass through the through holes and resisting the subsidiary element. The test machine provides a driven force to press the support board to separate the subsidiary element from the housing.

Abstract: A system (100) for managing fixture calibration report includes a database (40) and a server (30). The database stores basic information reports and measurement reports of fixtures. The server is connected to the database and includes a calibration report generating module (301) configured to acquire relational data from the measurement reports, calculate and estimate the relational data acquired from the measurement report in order to generate a calibration report for each fixture, and an information transfer module (307) configured to obtain an electronic information account from the basic information reports. The calibration report generating module (301) is further configured for sending the calibration reports to the obtained electronic information account. A method for managing fixture calibration reports is also provided.

Abstract: A positioning structure for a dual-use antenna and base includes a base having a narrow long hollow pipe wall and a wing board extended externally from two corresponding sides along the hollow pipe wall, and a hollow flange is disposed on the surface of the hollow pipe wall along the vertical direction of the two wing boards, and the back of the two wing boards is connected to a board body, and the board body includes at least one wall hanging hole, so that the base not only can be secured on a desktop, but also can be hanged on a wall by the wall hanging holes.

Abstract: A positioning structure for a dual-use antenna and base includes a base having a narrow long hollow pipe wall and a wing board extended externally from two corresponding sides along the hollow pipe wall, and a hollow flange is disposed on the surface of the hollow pipe wall along the vertical direction of the two wing boards, and the back of the two wing boards is connected to a board body, and the board body includes at least one wall hanging hole, so that the base not only can be secured on a desktop, but also can be hanged on a wall by the wall hanging holes.