Patents by Inventor Chun-Ying Wang

Chun-Ying Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250076369
    Abstract: A minimum IC operating voltage searching method includes acquiring a corner type of an IC, acquiring ring oscillator data of the IC, generating a first prediction voltage according to the corner type and the ring oscillator data by using a training model, generating a second prediction voltage according to the ring oscillator data by using a non-linear regression approach under an N-ordered polynomial, and generating a predicted minimum IC operating voltage according to the first prediction voltage and the second prediction voltage. N is a positive integer.
    Type: Application
    Filed: April 16, 2024
    Publication date: March 6, 2025
    Applicant: MEDIATEK INC.
    Inventors: Ronald Kuo-Hua Ho, Kun-Yu Wang, Yen-Chang Shih, Sung-Te Chen, Cheng-Han Wu, Yi-Ying Liao, Chun-Ming Huang, Yen-Feng Lu, Ching-Yu Tsai, Tai-Lai Tung, Kuan-Fu Lin, Bo-Kang Lai, Yao-Syuan Lee, Tsyr-Rou Lin, Ming-Chao Tsai, Li-Hsuan Chiu
  • Patent number: 12094727
    Abstract: A method forming a semiconductor package device includes: providing a substrate; forming a flip chip die on a first side on the substrate; and forming a molding compound on the first side of the substrate. The molding compound covers the flip chip die. The method further includes forming a heat sink on the molding compound; and forming a taping layer on a second side of the substrate, wherein the second side is opposite from the first side in a vertical direction. After forming the taping layer, the method further includes performing a pre-cut process and an etching process on the heat sink; and removing the taping layer.
    Type: Grant
    Filed: January 4, 2022
    Date of Patent: September 17, 2024
    Assignee: SILICON MOTION, INC.
    Inventors: Yi-Hung Chien, Chun-Ying Wang, Te-Wei Chen, Hsiu-Yuan Chen, Bing-Ling Wu
  • Publication number: 20230062499
    Abstract: A method forming a semiconductor package device includes: providing a substrate; forming a flip chip die on a first side on the substrate; and forming a molding compound on the first side of the substrate. The molding compound covers the flip chip die. The method further includes forming a heat sink on the molding compound; and forming a taping layer on a second side of the substrate, wherein the second side is opposite from the first side in a vertical direction. After forming the taping layer, the method further includes performing a pre-cut process and an etching process on the heat sink; and removing the taping layer.
    Type: Application
    Filed: January 4, 2022
    Publication date: March 2, 2023
    Inventors: Yi-Hung CHIEN, Chun-Ying WANG, Te-Wei CHEN, Hsiu-Yuan CHEN, Bing-Ling WU
  • Patent number: 10008501
    Abstract: The present disclosure relates to a transistor device having a channel region comprising a sandwich film stack with a plurality of different layers that improve device performance, and an associated apparatus. In some embodiments, the transistor device has a source region and a drain region disposed within a semiconductor substrate. A sandwich film stack is laterally positioned between the source region and the drain region. The sandwich film stack has a lower layer, a middle layer of a carbon doped semiconductor material disposed over the lower layer, and an upper layer disposed over the middle layer. A gate structure is disposed over the sandwich film stack. The gate structure is configured to control a flow of charge carriers in a channel region located between the source region and the drain region.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: June 26, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ru-Shang Hsiao, Ling-Sung Wang, Chih-Mu Huang, Cing-Yao Chan, Chun-Ying Wang, Jen-Pan Wang
  • Publication number: 20170005095
    Abstract: The present disclosure relates to a transistor device having a channel region comprising a sandwich film stack with a plurality of different layers that improve device performance, and an associated apparatus. In some embodiments, the transistor device has a source region and a drain region disposed within a semiconductor substrate. A sandwich film stack is laterally positioned between the source region and the drain region. The sandwich film stack has a lower layer, a middle layer of a carbon doped semiconductor material disposed over the lower layer, and an upper layer disposed over the middle layer. A gate structure is disposed over the sandwich film stack. The gate structure is configured to control a flow of charge carriers in a channel region located between the source region and the drain region.
    Type: Application
    Filed: September 16, 2016
    Publication date: January 5, 2017
    Inventors: Ru-Shang Hsiao, Ling-Sung Wang, Chih-Mu Huang, Cing-Yao Chan, Chun-Ying Wang, Jen-Pan Wang
  • Patent number: 9466670
    Abstract: The present disclosure relates to a method of forming a transistor device having a channel region comprising a sandwich film stack with a plurality of different layers that improve device performance, and an associated apparatus. In some embodiments, the method is performed by selectively etching a semiconductor substrate to form a recess along a top surface of the semiconductor substrate. A sandwich film stack having a plurality of nested layers is formed within the recess. At least two of the nested layers include different materials that improve different aspects of the performance of the transistor device. A gate structure is formed over the sandwich film stack. The gate structure controls the flow of charge carriers in a channel region having the sandwich film stack, which is laterally positioned between a source region and a drain region disposed within the semiconductor substrate.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: October 11, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ru-Shang Hsiao, Ling-Sung Wang, Chih-Mu Huang, Cing-Yao Chan, Chun-Ying Wang, Jen-Pan Wang
  • Patent number: 9287139
    Abstract: A method includes forming a dummy gate stack over a semiconductor substrate, removing the dummy gate stack to form a recess, and implanting a portion of the semiconductor substrate through the recess. During the implantation, an amorphous region is formed from the portion of the semiconductor substrate. The method further includes forming a strained capping layer, wherein the strained capping layer extends into the recess. An annealing is performed on the amorphous region to re-crystallize the amorphous region. The strained capping layer is then removed.
    Type: Grant
    Filed: February 21, 2014
    Date of Patent: March 15, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ru-Shang Hsiao, Cing-Yao Chan, Chun-Ying Wang, Jen-Pan Wang
  • Publication number: 20150263092
    Abstract: The present disclosure relates to a method of forming a transistor device having a channel region comprising a sandwich film stack with a plurality of different layers that improve device performance, and an associated apparatus. In some embodiments, the method is performed by selectively etching a semiconductor substrate to form a recess along a top surface of the semiconductor substrate. A sandwich film stack having a plurality of nested layers is formed within the recess. At least two of the nested layers include different materials that improve different aspects of the performance of the transistor device. A gate structure is formed over the sandwich film stack. The gate structure controls the flow of charge carriers in a channel region having the sandwich film stack, which is laterally positioned between a source region and a drain region disposed within the semiconductor substrate.
    Type: Application
    Filed: March 12, 2014
    Publication date: September 17, 2015
    Inventors: Ru-Shang Hsiao, Ling-Sung Wang, Chih-Mu Huang, Cing-Yao Chan, Chun-Ying Wang, Jen-Pan Wang
  • Publication number: 20150243526
    Abstract: A method includes forming a dummy gate stack over a semiconductor substrate, removing the dummy gate stack to form a recess, and implanting a portion of the semiconductor substrate through the recess. During the implantation, an amorphous region is formed from the portion of the semiconductor substrate. The method further includes forming a strained capping layer, wherein the strained capping layer extends into the recess. An annealing is performed on the amorphous region to re-crystallize the amorphous region. The strained capping layer is then removed.
    Type: Application
    Filed: February 21, 2014
    Publication date: August 27, 2015
    Inventors: Ru-Shang Hsiao, Cing-Yao Chan, Chun-Ying Wang, Jen-Pan Wang
  • Patent number: 7966891
    Abstract: A fatigue test apparatus for thin workpiece includes a supporting module, a driving mechanism, a first connecting module, a second connecting module, a first holding post, a second holding post and a computer system. The first and second connecting modules are respectively fixed to two sides of the supporting module. Ends of the first holding post and the second holding post are fixed to the first and second connecting modules. The computer system electronically connects with and controls the driving mechanism. The first holding post and the second holding post are drive to rotate by the driving mechanism.
    Type: Grant
    Filed: April 3, 2009
    Date of Patent: June 28, 2011
    Assignees: Shenzhen Futaigong Precision Industry Co., Ltd., FIH (Hong Kong) Limited
    Inventors: Lei Li, Ping Chen, Zhi-Qiang Jiang, Chun-Ying Wang, Xue-Liang Zhai, Li-Ping Huang, Zhi Cheng, Chang-Fa Sun, Xian-Cui Du
  • Publication number: 20090292498
    Abstract: A resistance testing device detects resistances between testing points of an electronic element. The resistance testing device includes controls accepting input of data to the resistance testing device, a relay module, a multimeter, testing probes electrically connected to the relay module, a testing platform including a base and a probe mounting board, a driving assembly mounted on the base and moving the probe mounting board relative to the electronic device, a display, and a central processing assembly mounted within the base. The relay module controls the testing probes and implements the multimeter to detect resistances between the testing points. The base seats the electronic element, the probe mounting board fixes the testing probes, and the probe mounting board is adjustably mounted above the base. The central processing assembly includes a central processing unit. The central processing unit is respectively and electronically connected to the controls, driving assembly, display and the relay module.
    Type: Application
    Filed: May 18, 2009
    Publication date: November 26, 2009
    Applicants: SHENZHEN FUTAIHONG PRECISION INDUSTRY CO., LTD., FIH (HONG KONG) LIMITED
    Inventors: LEI LI, LIN-SEN DONG, ZHI-QIANG JIANG, PING CHEN, ZHI CHENG, CHANG-FA SUN, CHUAN-KANG TAN, LIN LI, CHUN-YING WANG
  • Publication number: 20090260455
    Abstract: A test apparatus for testing a separation force between a housing (92) and a subsidiary element (94) of a portable electronic device (100). The housing defines a plurality of through holes. The subsidiary element is attached to the housing, and covers the through holes. The test apparatus includes: a positioning apparatus (50), a push mechanism (60) and a test machine (70). The positioning apparatus positions the housing with the subsidiary element therein. The push mechanism includes a support board (62) and a plurality of rods (64). The rods are mounted in the support board. The rods pass through the through holes and resisting the subsidiary element. The test machine provides a driven force to press the support board to separate the subsidiary element from the housing.
    Type: Application
    Filed: October 27, 2008
    Publication date: October 22, 2009
    Applicants: SHENZHEN FUTAIHONG PRECISION INDUSTRY CO., LTD., FIH (HONG KONG) LIMITED
    Inventors: LEI LI, PING CHEN, CHUN-YING WANG, SHU-ZHEN ZHANG, XIAO-HONG HUANG, CHEN-JING CAO
  • Publication number: 20090260451
    Abstract: A fatigue test apparatus for thin workpiece includes a supporting module, a driving mechanism, a first connecting module, a second connecting module, a first holding post, a second holding post and a computer system. The first and second connecting modules are respectively fixed to two sides of the supporting module. Ends of the first holding post and the second holding post are fixed to the first and second connecting modules. The computer system electronically connects with and controls the driving mechanism. The first holding post and the second holding post are drive to rotate by the driving mechanism.
    Type: Application
    Filed: April 3, 2009
    Publication date: October 22, 2009
    Applicants: SHENZHEN FUTAIHONG PRECISION INDUSTRY CO., LTD., FIH (HONG KONG) LIMITED
    Inventors: LEI LI, PING CHEN, ZHI-QIANG JIANG, CHUN-YING WANG, XUE-LIANG ZHAI, LI-PING HUANG, ZHI CHENG, CHANG-FA SUN, XIAN-CUI DU
  • Patent number: 7594444
    Abstract: A test apparatus for testing a separation force between a housing (92) and a subsidiary element (94) of a portable electronic device (100). The housing defines a plurality of through holes. The subsidiary element is attached to the housing, and covers the through holes. The test apparatus includes: a positioning apparatus (50), a push mechanism (60) and a test machine (70). The positioning apparatus positions the housing with the subsidiary element therein. The push mechanism includes a support board (62) and a plurality of rods (64). The rods are mounted in the support board. The rods pass through the through holes and resisting the subsidiary element. The test machine provides a driven force to press the support board to separate the subsidiary element from the housing.
    Type: Grant
    Filed: October 27, 2008
    Date of Patent: September 29, 2009
    Assignees: Shenzhen Futaihong Precision Industry Co., Ltd., FIH (Hong Kong) Limited
    Inventors: Lei Li, Ping Chen, Chun-Ying Wang, Shu-Zhen Zhang, Xiao-Hong Huang, Chen-Jing Cao
  • Publication number: 20080147782
    Abstract: A system (100) for managing fixture calibration report includes a database (40) and a server (30). The database stores basic information reports and measurement reports of fixtures. The server is connected to the database and includes a calibration report generating module (301) configured to acquire relational data from the measurement reports, calculate and estimate the relational data acquired from the measurement report in order to generate a calibration report for each fixture, and an information transfer module (307) configured to obtain an electronic information account from the basic information reports. The calibration report generating module (301) is further configured for sending the calibration reports to the obtained electronic information account. A method for managing fixture calibration reports is also provided.
    Type: Application
    Filed: August 1, 2007
    Publication date: June 19, 2008
    Applicants: SHENZHEN FUTAIHONG PRECISION INDUSTRY CO., LTD., SUTECH TRADING LIMITED
    Inventors: LEI LI, PING CHEN, LIANG-LIANG SONG, LI-SHA CHEN, HAN-YING CHEN, CHUN-YING WANG
  • Patent number: 7209095
    Abstract: A positioning structure for a dual-use antenna and base includes a base having a narrow long hollow pipe wall and a wing board extended externally from two corresponding sides along the hollow pipe wall, and a hollow flange is disposed on the surface of the hollow pipe wall along the vertical direction of the two wing boards, and the back of the two wing boards is connected to a board body, and the board body includes at least one wall hanging hole, so that the base not only can be secured on a desktop, but also can be hanged on a wall by the wall hanging holes.
    Type: Grant
    Filed: September 9, 2005
    Date of Patent: April 24, 2007
    Assignee: Lanready Technologies, Inc.
    Inventor: Chun-Ying Wang
  • Publication number: 20070057863
    Abstract: A positioning structure for a dual-use antenna and base includes a base having a narrow long hollow pipe wall and a wing board extended externally from two corresponding sides along the hollow pipe wall, and a hollow flange is disposed on the surface of the hollow pipe wall along the vertical direction of the two wing boards, and the back of the two wing boards is connected to a board body, and the board body includes at least one wall hanging hole, so that the base not only can be secured on a desktop, but also can be hanged on a wall by the wall hanging holes.
    Type: Application
    Filed: September 9, 2005
    Publication date: March 15, 2007
    Applicant: LANREADY TECHNOLOGIES INC.
    Inventor: Chun-Ying Wang