Patents by Inventor Chunyuan Qi

Chunyuan Qi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240266393
    Abstract: A metasurface structure includes a substrate having a first region and a second region not overlapping with the first region; a first pillar element within the first region on the substrate; and a second pillar element within the second region on the substrate. The first pillar element has a first sectional profile and the second pillar element has a second sectional profile that is different from the first sectional profile. At least one of the first sectional profile and the second sectional profile is of a non-rectangular shape.
    Type: Application
    Filed: March 9, 2023
    Publication date: August 8, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: CHUNYUAN QI, XINGXING CHEN, ZHUONA MA, HUI LIU
  • Publication number: 20230154926
    Abstract: Provided are a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a carrier substrate, a trap-rich layer, a dielectric layer, an interconnect structure, a device structure layer and a circuit structure. The trap-rich layer is disposed on the carrier substrate. The dielectric layer is disposed on the trap-rich layer. The interconnect structure is disposed on the dielectric layer. The device structure layer is disposed on the interconnect structure and electrically connected to the interconnect structure. The circuit structure is disposed on the device structure layer and electrically connected to the device structure layer.
    Type: Application
    Filed: January 11, 2023
    Publication date: May 18, 2023
    Inventors: Sheng Zhang, Chunyuan QI, Xingxing Chen, Chien-Kee Pang
  • Publication number: 20230094739
    Abstract: An silicon-on-insulator substrate is provided in the present invention, including a handler, a polysilicon trap-rich layer formed on the handler, an oxide layer formed on the polysilicon trap-rich layer and a monocrystalline silicon layer formed directly on the oxide layer, wherein a bonding interface is between the monocrystalline silicon layer and the oxide layer.
    Type: Application
    Filed: October 26, 2021
    Publication date: March 30, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: CHUNYUAN QI, Sheng Zhang, XINGXING CHEN, Chien-Kee Pang
  • Patent number: 11605648
    Abstract: Provided are a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a carrier substrate, a trap-rich layer, a dielectric layer, an interconnect structure, a device structure layer and a circuit structure. The trap-rich layer is disposed on the carrier substrate. The dielectric layer is disposed on the trap-rich layer. The interconnect structure is disposed on the dielectric layer. The device structure layer is disposed on the interconnect structure and electrically connected to the interconnect structure. The circuit structure is disposed on the device structure layer and electrically connected to the device structure layer.
    Type: Grant
    Filed: July 22, 2021
    Date of Patent: March 14, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Sheng Zhang, Chunyuan Qi, Xingxing Chen, Chien-Kee Pang
  • Publication number: 20220415926
    Abstract: Provided are a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a carrier substrate, a trap-rich layer, a dielectric layer, an interconnect structure, a device structure layer and a circuit structure. The trap-rich layer is disposed on the carrier substrate. The dielectric layer is disposed on the trap-rich layer. The interconnect structure is disposed on the dielectric layer. The device structure layer is disposed on the interconnect structure and electrically connected to the interconnect structure. The circuit structure is disposed on the device structure layer and electrically connected to the device structure layer.
    Type: Application
    Filed: July 22, 2021
    Publication date: December 29, 2022
    Applicant: United Microelectronics Corp.
    Inventors: Sheng Zhang, Chunyuan Qi, Xingxing Chen, Chien-Kee Pang