Abstract: An multiplier circuit that generates a negate product -B*C quickly without requiring a separate negate operation. This multiplier circuit uses partial product multiplication and any of a variety of multiplication techniques, such as bit-pair recoding or the Booth algorithm, to perform multiplication and negate multiplication operations. The multiplier circuit uses an encoder circuit to produce encoded multiplier strings in accordance with such multiplication techniques. The multiplier circuit reorders bits of such encoded multiplier strings to cause a binary multiplier circuit to generate the negate product -B*C rather than the product B*C. The reordering can be accomplished in any manner, such as by a bus coupling the encoder circuit to the binary multiplier circuit. The encoder circuit can be coupled to the binary multiplier circuit using two buses and a multiplexor circuit.